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/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/
Dxtensa_loadstore_handler.S2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
4 * SPDX-License-Identifier: Apache-2.0
17 * -------------------
22 * -----------------------------
23 * L8UI xxxx xxxx 0000 ssss tttt 0010 <- LoadStoreError
24 …* L16UI xxxx xxxx 0001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignme…
25 …* L16SI xxxx xxxx 1001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignme…
26 * L32I xxxx xxxx 0010 ssss tttt 0010 <- LoadStoreAlignment
28 * S8I xxxx xxxx 0100 ssss tttt 0010 <- LoadStoreError
29 …* S16I xxxx xxxx 0101 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignme…
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Dxtensa_vectors.S2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
4 * SPDX-License-Identifier: MIT
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
9 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
32 --------------------------------------------------------------------------------
43 Users can install application-specific interrupt handlers for low and
50 dispatched to the RTOS-specific handler. This timer cannot be hooked
54 run-time, made available by compiling this source file with
55 '-DXT_INTEXC_HOOKS' (useful for automated testing).
61 Users can also install application-specific exception handlers in the
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/Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/
Dxtensa_vectors.S3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
40 Users can install application-specific interrupt handlers for low and
47 dispatched to the RTOS-specific handler. This timer cannot be hooked
51 run-time, made available by compiling this source file with
52 '-DXT_INTEXC_HOOKS' (useful for automated testing).
58 Users can also install application-specific exception handlers in the
82 NOTES on the use of 'call0' for long jumps instead of 'j':
83 1. This file should be assembled with the -mlongcalls option to xt-xcc.
84 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
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/Kernel-v11.1.0/.github/workflows/
Dkernel-demos.yml1 name: FreeRTOS-Kernel Demos
6 bashPass: \033[32;1mPASSED -
7 bashInfo: \033[33;1mINFO -
8 bashFail: \033[31;1mFAILED -
12 WIN32-MSVC:
14 runs-on: windows-latest
16 - name: Checkout the FreeRTOS/FreeRTOS Repository
22 fetch-depth: 1
25 - name: Checkout Pull Request
30 - name: Add msbuild to PATH
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Dcoverity_scan.yml10 bashPass: \033[32;1mPASSED -
11 bashInfo: \033[33;1mINFO -
12 bashFail: \033[31;1mFAILED -
16 Coverity-Scan:
17 if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' )
19 runs-on: ubuntu-latest
21 - name: Checkout the Repository
24 - env:
29 echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
31 sudo apt-get -y update
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/Kernel-v11.1.0/portable/IAR/RISC-V/
DportASM.s5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
34 * + The code that is common to all RISC-V chips is implemented in
35 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
36 * portASM.S file because the same file is used no matter which RISC-V chip is
39 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
42 * RISC-V chip that both includes a standard CLINT and does not add to the
43 * base set of RISC-V registers. There are additional
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/Kernel-v11.1.0/portable/GCC/RISC-V/
DportASM.S5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
34 * + The code that is common to all RISC-V chips is implemented in
35 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
36 * portASM.S file because the same file is used no matter which RISC-V chip is
39 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
42 * RISC-V chip that both includes a standard CLINT and does not add to the
43 * base set of RISC-V registers. There are additional
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/Kernel-v11.1.0/portable/ThirdParty/GCC/ARC_v1/
Darc_support.s5 * SPDX-License-Identifier: MIT
38 * core-dependent part in assemble language (for arc)
53 * the pre-conditions of this routine are task context, CPU is
65 j [blink]
74 * this routine is called in the non-task context during the startup of the kernel
92 st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */
116 j [r0]
130 j [r1]
178 ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
205 bl dispatcher /* r0->pxCurrentTCB */
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/Kernel-v11.1.0/portable/ThirdParty/GCC/ARC_EM_HS/
Darc_support.s5 * SPDX-License-Identifier: MIT
38 * core-dependent part in assemble language (for arc)
53 * the pre-conditions of this routine are task context, CPU is
65 j [blink]
74 * this routine is called in the non-task context during the startup of the kernel
92 st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */
128 j [r0]
142 j [r1]
185 ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
208 bl dispatcher /* r0->pxCurrentTCB */
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/Kernel-v11.1.0/
DHistory.txt5 + Add ARMv7-R port with Memory Protection Unit (MPU) support.
6 + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
8 buffer when a task reads from a non-empty buffer:
9 - The task reading from a non-empty stream buffer returns immediately
11 - The task reading from a non-empty steam batching buffer blocks until the
37 + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
39 + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
43 compilers. We thank @Forty-Bot for their contribution.
54 POSIX timers to address issues with signal handling in non-FreeRTOS
56 + Update ARM_TFM port to support TF-Mv2.0.0 release of trusted-firmware-m.
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