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/Kernel-v11.0.1/include/
Dqueue.h5 * SPDX-License-Identifier: MIT
37 /* *INDENT-OFF* */
41 /* *INDENT-ON* */
93 * memory. The first block is used to hold the queue's data structures. The
102 * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
135 * // These should be passed by pointer as they contain a lot of data.
167 * memory. The first block is used to hold the queue's data structures. The
176 * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
188 * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is
192 * will be used to hold the queue's data structure.
[all …]
Dcroutine.h5 * SPDX-License-Identifier: MIT
38 /* *INDENT-OFF* */
42 /* *INDENT-ON* */
44 /* Used to hide the implementation of the co-routine control block. The
46 * the macro implementation of the co-routine functionality. */
49 /* Defines the prototype to which co-routine functions must conform. */
58 …UBaseType_t uxPriority; /**< The priority of the co-routine in relation to other co-routines.…
59 …Index; /**< Used to distinguish between co-routines when multiple co-routines use the same…
60 uint16_t uxState; /**< Used internally by the co-routine implementation. */
61 } CRCB_t; /* Co-routine control block. Note must be identical in size down …
[all …]
Dsemphr.h5 * SPDX-License-Identifier: MIT
53 * https://www.FreeRTOS.org/RTOS-task-notifications.html
63 * The queue length is 1 as this is a binary semaphore. The data size is 0
64 * as we don't want to actually store any data - we just want to know if the
118 * https://www.FreeRTOS.org/RTOS-task-notifications.html
144 * hold the semaphore's data structures could not be allocated.
181 * https://www.FreeRTOS.org/RTOS-task-notifications.html
200 * which will then be used to hold the semaphore's data structure, removing the
214 * // The semaphore's data structures will be placed in the xSemaphoreBuffer
244 * @param xSemaphore A handle to the semaphore being taken - obtained when
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/Kernel-v11.0.1/.github/workflows/
Dcoverity_scan.yml10 bashPass: \033[32;1mPASSED -
11 bashInfo: \033[33;1mINFO -
12 bashFail: \033[31;1mFAILED -
16 Coverity-Scan:
17 if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' )
19 runs-on: ubuntu-latest
21 - name: Checkout the Repository
24 - env:
29 echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
31 sudo apt-get -y update
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/Kernel-v11.0.1/portable/Renesas/RX100/
Dport.c5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
46 /*-----------------------------------------------------------*/
73 /*-----------------------------------------------------------*/
81 /*-----------------------------------------------------------*/
84 * Function to start the first task executing - written in asm code as direct
119 * executes the pre and post sleep macros, and actually calls the wait
126 /*-----------------------------------------------------------*/
132 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/GCC/TriCore_1782/
Dport.c5 * SPDX-License-Identifier: MIT
46 …/* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxT…
50 /*-----------------------------------------------------------*/
66 /* Each CSA contains 16 words of data. */
71 /*-----------------------------------------------------------*/
89 /*-----------------------------------------------------------*/
97 /*-----------------------------------------------------------*/
106 /* 16 Address Registers (4 Address registers are global), 16 Data in pxPortInitialiseStack()
111 * PCX for the task needs to point to Lower->Upper->NULL arrangement. in pxPortInitialiseStack()
115 * The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL. in pxPortInitialiseStack()
[all …]
/Kernel-v11.0.1/portable/GCC/RX100/
Dport.c5 * SPDX-License-Identifier: MIT
29 /*-----------------------------------------------------------
31 *----------------------------------------------------------*/
53 /*-----------------------------------------------------------*/
76 * priority - ie a known priority. Therefore these local macros are a slight
87 /*-----------------------------------------------------------*/
90 * Function to start the first task executing - written in asm code as direct
142 * executes the pre and post sleep macros, and actually calls the wait
149 /*-----------------------------------------------------------*/
159 /* Holds the maximum number of ticks that can be suppressed - which is
[all …]
/Kernel-v11.0.1/
Dqueue.c5 * SPDX-License-Identifier: MIT
52 #define queueUNLOCKED ( ( int8_t ) -1 )
80 /* Semaphores do not actually store or copy data, so have an item size of
101 * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
110 …QueuePointers_t xQueue; /**< Data required exclusively when this structure is used as a queue.…
111 …SemaphoreData_t xSemaphore; /**< Data required exclusively when this structure is used as a semaph…
114 …List_t xTasksWaitingToSend; /**< List of tasks that are blocked waiting to post onto t…
142 /*-----------------------------------------------------------*/
169 /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
186 * Uses a critical section to determine if there is any data in a queue.
[all …]
DHistory.txt35 was last assigned to the task - which due to priority inheritance, may not
42 FreeRTOSConfig.h. We thank @mdnr-g for their contribution.
46 vTaskResume or vTaskResumeFromISR. We thank @Moral-Hao for their
49 FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices.
54 + Add CMake support to allow the application writer to select the RISC-V
58 + Make taskYIELD available to unprivileged tasks for ARMv8-M ports.
59 + Update Cortex-M23 ports to not use PSPLIM_NS. We thank @urutva for their
61 + Update the SysTick setup code for ARMv8-M ports to first configure the clock
66 + Add the port-optimized task selection algorithm optionally available for
67 ARMv7-M ports to the ARMv8-M ports. We thank @jefftenney for their
[all …]
Dtasks.c5 * SPDX-License-Identifier: MIT
54 * to generate human readable text from the raw data generated by the
82 if( pxCurrentTCB->uxPriority < ( pxTCB )->uxPriority ) \
95 …#define taskYIELD_TASK_CORE_IF_USING_PREEMPTION( pxTCB ) prvYieldCore( ( pxTCB )->xTaskRunState…
139 * Some kernel aware debuggers require the data the debugger needs access to to
168 /*-----------------------------------------------------------*/
179 --uxTopPriority; \
193 /*-----------------------------------------------------------*/
210 /*-----------------------------------------------------------*/
222 /*-----------------------------------------------------------*/
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/Kernel-v11.0.1/portable/GCC/ARM_CM55_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CM85/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CM85_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM85_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM35P_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM55/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM33_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM35P/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM23_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM33/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CM35P_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CM55/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CM33_NTZ/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/GCC/ARM_CM35P/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]
/Kernel-v11.0.1/portable/IAR/ARM_CM23/non_secure/
Dport.c5 * SPDX-License-Identifier: MIT
55 * i.e. the processor boots as secure and never jumps to the non-secure side.
62 * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
65 * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
73 * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23
81 /*-----------------------------------------------------------*/
87 /*-----------------------------------------------------------*/
105 /*-----------------------------------------------------------*/
113 /*-----------------------------------------------------------*/
120 /*-----------------------------------------------------------*/
[all …]

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