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/Kernel-v11.1.0/portable/GCC/ARM_CRx_MPU/
Dmpu_wrappers_v2_asm.S5 * SPDX-License-Identifier: MIT
29 /* ----------------------------------------------------------------------------------- */
41 /* ----------------------- Start of Port Specific System Calls ----------------------- */
47 .global vPortYield
53 /* ----------------------------------------------------------------------------------- */
59 .global vPortSystemCallExit
65 /* ----------------------------------------------------------------------------------- */
71 * - Return value must be in R0.
74 .global xPortIsPrivileged
84 /* ----------------------------------------------------------------------------------- */
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DportASM.S5 * SPDX-License-Identifier: MIT
38 /* External FreeRTOS-Kernel variables. */
48 /* External FreeRTOS-Kernel functions. */
52 /* ----------------------------------------------------------------------------------- */
72 VSTM LR!, { D0-D15 } /* Store D0-D15. */
75 POP { R0 } /* Restore R0 to pre-exception value. */
76 /* STM (user registers) - In a PL1 mode other than System mode, STM (user
84 * - The macro portSAVE_CONTEXT MUST be called from a PL1 mode other than
86 * - Base register LR of the current mode will be used which contains the
88 * - It will store R0-R14 of User mode i.e. pre-exception SP(R13) and LR(R14)
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/Kernel-v11.1.0/portable/ThirdParty/GCC/Xtensa_ESP32/
Dxtensa_vector_defaults.S2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
4 * SPDX-License-Identifier: Apache-2.0
24 .global xt_debugexception
110 1: addi a0, a0, -1 /* delay_us(N) */
123 .global xt_highint2
141 .global xt_highint3
160 .global xt_highint4
179 .global xt_highint5
199 .global _xt_highint6
200 .global xt_highint6
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Dxtensa_vectors.S2 * SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
4 * SPDX-License-Identifier: MIT
6 * SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
9 * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
32 --------------------------------------------------------------------------------
43 Users can install application-specific interrupt handlers for low and
50 dispatched to the RTOS-specific handler. This timer cannot be hooked
54 run-time, made available by compiling this source file with
55 '-DXT_INTEXC_HOOKS' (useful for automated testing).
61 Users can also install application-specific exception handlers in the
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/Kernel-v11.1.0/portable/CodeWarrior/ColdFire_V1/
Dportasm.S5 * SPDX-License-Identifier: MIT
38 .global ulPortSetIPL
39 .global _ulPortSetIPL
40 .global mcf5xxx_wr_cacrx
41 .global _mcf5xxx_wr_cacrx
42 .global vPortYieldISR
43 .global _vPortYieldISR
44 .global vPortStartFirstTask
45 .global _vPortStartFirstTask
53 lea.l (-60, sp), sp
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/Kernel-v11.1.0/portable/CodeWarrior/ColdFire_V2/
Dportasm.S5 * SPDX-License-Identifier: MIT
38 .global ulPortSetIPL
39 .global _ulPortSetIPL
40 .global mcf5xxx_wr_cacrx
41 .global _mcf5xxx_wr_cacrx
42 .global vPortYieldISR
43 .global _vPortYieldISR
44 .global vPortStartFirstTask
45 .global _vPortStartFirstTask
53 lea.l (-60, sp), sp
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/Kernel-v11.1.0/portable/MPLAB/PIC32MZ/
Dport_asm.S5 * SPDX-License-Identifier: MIT
40 .global vPortStartFirstTask
41 .global vPortYieldISR
42 .global vPortTickInterruptHandler
43 .global vPortInitialiseFPSCR
60 .global __vector_dispatch_0
64 .global __vector_dispatch_4
68 .global __vector_dispatch_9
72 .global __vector_dispatch_14
76 .global __vector_dispatch_19
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/Kernel-v11.1.0/portable/Tasking/ARM_CM4F/
Dport_asm.asm5 ; * SPDX-License-Identifier: MIT
34 .global _vector_14
35 .global _lc_ref__vector_pp_14
36 .global SVC_Handler
37 .global vPortStartFirstTask
38 .global vPortEnableVFP
39 .global ulPortSetInterruptMask
40 .global vPortClearInterruptMask
42 ;-----------------------------------------------------------
59 vstmdbeq r0!, {s16-s31}
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/Kernel-v11.1.0/portable/ThirdParty/XCC/Xtensa/
Dxtensa_intr_asm.S3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
43 -------------------------------------------------------------------------------
45 -------------------------------------------------------------------------------
49 .global _xt_intdata
52 .global _xt_intenable
55 .global _xt_vpri_mask
64 -------------------------------------------------------------------------------
65 Table of C-callable interrupt handlers for each interrupt. Note that not all
68 -------------------------------------------------------------------------------
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Dxtensa_vectors.S3 * Copyright (C) 2015-2019 Cadence Design Systems, Inc.
6 * SPDX-License-Identifier: MIT
40 Users can install application-specific interrupt handlers for low and
47 dispatched to the RTOS-specific handler. This timer cannot be hooked
51 run-time, made available by compiling this source file with
52 '-DXT_INTEXC_HOOKS' (useful for automated testing).
58 Users can also install application-specific exception handlers in the
83 1. This file should be assembled with the -mlongcalls option to xt-xcc.
84 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
91 has a longer range than 'j' due to the target being word-aligned, so
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/Kernel-v11.1.0/portable/CCS/MSP430X/
Dportext.asm5 ; * SPDX-License-Identifier: MIT
34 .global xTaskIncrementTick
35 .global vTaskSwitchContext
36 .global vPortSetupTimerInterrupt
37 .global pxCurrentTCB
38 .global usCriticalNesting
45 ;-----------------------------------------------------------
56 ;-----------------------------------------------------------
70 ;-----------------------------------------------------------
96 ;-----------------------------------------------------------
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/Kernel-v11.1.0/portable/GCC/IA32_flat/
DportASM.S5 * SPDX-License-Identifier: MIT
41 .global vPortStartFirstTask
42 .global vPortCentralInterruptWrapper
43 .global vPortAPICErrorHandlerWrapper
44 .global vPortTimerHandler
45 .global vPortYieldCall
46 .global vPortAPICSpuriousHandler
50 /*-----------------------------------------------------------*/
83 /* Find the location of pxCurrentTCB again - a callee saved register could
107 /*-----------------------------------------------------------*/
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/Kernel-v11.1.0/.github/
DCODEOWNERS5 # @global-owner1 and @global-owner2 will be requested for
7 * @FreeRTOS/pr-bar-raiser
11 # modifies JS files, only @js-owner and not the global
13 # *.c FreeRTOS/pr-bar-raiser
26 # `docs/getting-started.md` but not further nested files like
27 # `docs/build-app/troubleshooting.md`.
/Kernel-v11.1.0/portable/GCC/PPC440_Xilinx/
Dportasm.S5 * SPDX-License-Identifier: MIT
36 .global vPortStartFirstTask
37 .global vPortYield
38 .global vPortTickISR
39 .global vPortISRWrapper
40 .global vPortSaveFPURegisters
41 .global vPortRestoreFPURegisters
55 .set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
69 stwu R1, -24( R1 )
83 lwz R31, -4( R11 )
/Kernel-v11.1.0/portable/GCC/PPC405_Xilinx/
Dportasm.S5 * SPDX-License-Identifier: MIT
36 .global vPortStartFirstTask
37 .global vPortYield
38 .global vPortTickISR
39 .global vPortISRWrapper
40 .global vPortSaveFPURegisters
41 .global vPortRestoreFPURegisters
55 .set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
69 stwu R1, -24( R1 )
83 lwz R31, -4( R11 )
/Kernel-v11.1.0/portable/MPLAB/PIC32MEC14xx/
Dport_asm.S5 * SPDX-License-Identifier: MIT
45 .global vPortStartFirstTask .text
46 .global vPortYieldISR .text
47 .global vPortTickInterruptHandler .text
56 * MEC14xx - This ISR will only be used if HW timers' interrupts
134 .global vPortYieldISR
138 .global girq24_isr
156 .global girq24_b1
165 addiu sp, sp, -portCONTEXT_SIZE
174 /* Prepare to re-enable interrupts above the kernel priority. */
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/Kernel-v11.1.0/portable/GCC/ColdFire_V2/
Dportasm.S5 * SPDX-License-Identifier: MIT
38 .global ulPortSetIPL
39 .global mcf5xxx_wr_cacr
40 .global __cs3_isr_interrupt_80
41 .global vPortStartFirstTask
47 lea.l (-60, %sp), %sp
48 movem.l %d0-%fp, (%sp)
58 movem.l (%sp), %d0-%fp
76 link A6,#-8
77 movem.l D6-D7,(SP)
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/Kernel-v11.1.0/portable/ThirdParty/GCC/ARC_v1/
Darc_support.s5 * SPDX-License-Identifier: MIT
38 * core-dependent part in assemble language (for arc)
50 .global dispatch
53 * the pre-conditions of this routine are task context, CPU is
70 .global start_dispatch
74 * this routine is called in the non-task context during the startup of the kernel
92 st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */
123 .global start_r
134 .global exc_entry_cpu
178 ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
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/Kernel-v11.1.0/portable/GCC/RL78/
Dportasm.S5 * SPDX-License-Identifier: MIT
32 .global _vPortYield
33 .global _vPortStartFirstTask
34 .global _vPortTickISR
/Kernel-v11.1.0/portable/GCC/RISC-V/
DportASM.S5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
34 * + The code that is common to all RISC-V chips is implemented in
35 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
36 * portASM.S file because the same file is used no matter which RISC-V chip is
39 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
42 * RISC-V chip that both includes a standard CLINT and does not add to the
43 * base set of RISC-V registers. There are additional
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/Kernel-v11.1.0/portable/ThirdParty/GCC/ARC_EM_HS/
Darc_support.s5 * SPDX-License-Identifier: MIT
38 * core-dependent part in assemble language (for arc)
50 .global dispatch
53 * the pre-conditions of this routine are task context, CPU is
70 .global start_dispatch
74 * this routine is called in the non-task context during the startup of the kernel
92 st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */
135 .global start_r
146 .global exc_entry_cpu
185 ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
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/Kernel-v11.1.0/portable/GCC/MicroBlazeV8/
Dportasm.S5 * SPDX-License-Identifier: MIT
40 #define portMINUS_CONTEXT_SIZE -136
43 #define portMINUS_CONTEXT_SIZE -132
90 .global _interrupt_handler
91 .global VPortYieldASM
92 .global vPortStartFirstTask
93 .global vPortExceptionHandlerEntry
217 /* Return using rtid so interrupts are re-enabled as this function is
/Kernel-v11.1.0/portable/ThirdParty/CDK/T-HEAD_CK802/
Dportasm.S2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * SPDX-License-Identifier: MIT
31 .global vPortStartTask
44 ldm r0-r13, (sp)
52 .global vPortYield
57 stm r0-r13, (sp)
78 ldm r0-r13, (sp)
87 .global NOVIC_IRQ_Default_Handler
92 stm r0-r13, (sp)
124 ldm r0-r13, (sp)
/Kernel-v11.1.0/portable/GCC/MicroBlaze/
Dportasm.s5 * SPDX-License-Identifier: MIT
34 .global __FreeRTOS_interrupt_handler
35 .global VPortYieldASM
36 .global vStartFirstTask
41 addik r1, r1, -132
44 /* Copy the msr into r31 - this is stacked later. */
/Kernel-v11.1.0/portable/GCC/MicroBlazeV9/
Dportasm.S5 * SPDX-License-Identifier: MIT
42 #define portMINUS_CONTEXT_SIZE -272
45 #define portMINUS_CONTEXT_SIZE -264
50 #define portMINUS_CONTEXT_SIZE -136
53 #define portMINUS_CONTEXT_SIZE -132
138 .global _interrupt_handler
139 .global VPortYieldASM
140 .global vPortStartFirstTask
141 .global vPortExceptionHandlerEntry
216 /* Restore the stack limits -- must not load from r1 (Stack Pointer)
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