1 /**************************************************************************//** 2 * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without modification, 5 * are permitted provided that the following conditions are met: 6 * 1. Redistributions of source code must retain the above copyright notice, 7 * this list of conditions and the following disclaimer. 8 * 2. Redistributions in binary form must reproduce the above copyright notice, 9 * this list of conditions and the following disclaimer in the documentation 10 * and/or other materials provided with the distribution. 11 * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors 12 * may be used to endorse or promote products derived from this software 13 * without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 *****************************************************************************/ 26 #include "M480.h" 27 #ifndef _M480_ETH_ 28 #define _M480_ETH_ 29 30 /* Generic MII registers. */ 31 32 #define MII_BMCR 0x00 /* Basic mode control register */ 33 #define MII_BMSR 0x01 /* Basic mode status register */ 34 #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 35 #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 36 #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 37 #define MII_LPA 0x05 /* Link partner ability reg */ 38 #define MII_EXPANSION 0x06 /* Expansion register */ 39 #define MII_DCOUNTER 0x12 /* Disconnect counter */ 40 #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 41 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 42 #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 43 #define MII_SREVISION 0x16 /* Silicon revision */ 44 #define MII_RESV1 0x17 /* Reserved... */ 45 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 46 #define MII_PHYADDR 0x19 /* PHY address */ 47 #define MII_RESV2 0x1a /* Reserved... */ 48 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 49 #define MII_NCONFIG 0x1c /* Network interface config */ 50 51 /* Basic mode control register. */ 52 #define BMCR_RESV 0x007f /* Unused... */ 53 #define BMCR_CTST 0x0080 /* Collision test */ 54 #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 55 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 56 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ 57 #define BMCR_PDOWN 0x0800 /* Power down the DP83840 */ 58 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 59 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 60 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 61 #define BMCR_RESET 0x8000 /* Reset the DP83840 */ 62 63 /* Basic mode status register. */ 64 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 65 #define BMSR_JCD 0x0002 /* Jabber detected */ 66 #define BMSR_LSTATUS 0x0004 /* Link status */ 67 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 68 #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 69 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 70 #define BMSR_RESV 0x07c0 /* Unused... */ 71 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 72 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 73 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 74 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 75 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 76 77 /* Advertisement control register. */ 78 #define ADVERTISE_SLCT 0x001f /* Selector bits */ 79 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 80 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 81 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 82 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 83 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 84 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 85 #define ADVERTISE_RESV 0x1c00 /* Unused... */ 86 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 87 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 88 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 89 90 #define RX_DESCRIPTOR_NUM 4 /*8 // Max Number of Rx Frame Descriptors */ 91 #define TX_DESCRIPTOR_NUM 2 /*4 // Max number of Tx Frame Descriptors */ 92 93 #define PACKET_BUFFER_SIZE 1520 94 95 #define CONFIG_PHY_ADDR 1 96 97 98 /* Frame Descriptor's Owner bit */ 99 #define OWNERSHIP_EMAC 0x80000000 /* 1 = EMAC */ 100 /*#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU */ 101 102 103 104 /* Rx Frame Descriptor Status */ 105 #define RXFD_RXGD 0x00100000 /* Receiving Good Packet Received */ 106 #define RXFD_RTSAS 0x00800000 /* RX Time Stamp Available */ 107 108 109 /* Tx Frame Descriptor's Control bits */ 110 #define TXFD_TTSEN 0x08 /* Tx Time Stamp Enable */ 111 #define TXFD_INTEN 0x04 /* Interrupt Enable */ 112 #define TXFD_CRCAPP 0x02 /* Append CRC */ 113 #define TXFD_PADEN 0x01 /* Padding Enable */ 114 115 /* Tx Frame Descriptor Status */ 116 #define TXFD_TXCP 0x00080000 /* Transmission Completion */ 117 #define TXFD_TTSAS 0x08000000 /* TX Time Stamp Available */ 118 119 /* Tx/Rx buffer descriptor structure */ 120 struct eth_descriptor; 121 struct eth_descriptor 122 { 123 uint32_t status1; 124 uint8_t * buf; 125 uint32_t status2; 126 struct eth_descriptor * next; 127 #ifdef TIME_STAMPING 128 uint32_t backup1; 129 uint32_t backup2; 130 uint32_t reserved1; 131 uint32_t reserved2; 132 #endif 133 }; 134 135 #ifdef TIME_STAMPING 136 137 #define ETH_TS_ENABLE() do { EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk; } while( 0 ) 138 #define ETH_TS_START() do { EMAC->TSCTL |= ( EMAC_TSCTL_TSMODE_Msk | EMAC_TSCTL_TSIEN_Msk ); } while( 0 ) 139 s32_t ETH_settime( u32_t sec, 140 u32_t nsec ); 141 s32_t ETH_gettime( u32_t * sec, 142 u32_t * nsec ); 143 s32_t ETH_updatetime( u32_t neg, 144 u32_t sec, 145 u32_t nsec ); 146 s32_t ETH_adjtimex( int ppm ); 147 void ETH_setinc( void ); 148 149 #endif /* ifdef TIME_STAMPING */ 150 151 #ifdef NU_TRACE 152 #define NU_DEBUGF( x ) { printf x; } 153 #else 154 #define NU_DEBUGF( x ) 155 #endif 156 157 void numaker_set_mac_addr( uint8_t * addr ); 158 int numaker_eth_init( uint8_t * mac_addr ); 159 uint8_t * numaker_eth_get_tx_buf( void ); 160 void numaker_eth_trigger_tx( uint16_t length, 161 void * p ); 162 int numaker_eth_get_rx_buf( uint16_t * len, 163 uint8_t ** buf ); 164 void numaker_eth_rx_next( void ); 165 void numaker_eth_trigger_rx( void ); 166 int numaker_eth_link_ok( void ); 167 void numaker_mac_address( uint8_t * mac ); 168 void numaker_eth_enable_interrupts( void ); 169 void numaker_eth_disable_interrupts( void ); 170 171 #endif /* _M480_ETH_ */ 172
xref:
/FreeRTOS-Plus-TCP-v4.0.0/source/portable/NetworkInterface/M487/m480_eth.h
(revision a4124602cc584fa0658448c229f48a459a84fbb1)