1 /* 2 * FreeRTOS Kernel V11.1.0 3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy of 8 * this software and associated documentation files (the "Software"), to deal in 9 * the Software without restriction, including without limitation the rights to 10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of 11 * the Software, and to permit persons to whom the Software is furnished to do so, 12 * subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in all 15 * copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS 19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR 20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * https://www.FreeRTOS.org 25 * https://github.com/FreeRTOS 26 * 27 */ 28 29 #ifndef PORTMACRO_H 30 #define PORTMACRO_H 31 32 /* *INDENT-OFF* */ 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 /* *INDENT-ON* */ 37 38 /*------------------------------------------------------------------------------ 39 * Port specific definitions. 40 * 41 * The settings in this file configure FreeRTOS correctly for the given hardware 42 * and compiler. 43 * 44 * These settings should not be altered. 45 *------------------------------------------------------------------------------ 46 */ 47 48 #ifndef configENABLE_MPU 49 #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. 50 #endif /* configENABLE_MPU */ 51 52 /*-----------------------------------------------------------*/ 53 54 /** 55 * @brief Type definitions. 56 */ 57 #define portCHAR char 58 #define portFLOAT float 59 #define portDOUBLE double 60 #define portLONG long 61 #define portSHORT short 62 #define portSTACK_TYPE uint32_t 63 #define portBASE_TYPE long 64 65 typedef portSTACK_TYPE StackType_t; 66 typedef long BaseType_t; 67 typedef unsigned long UBaseType_t; 68 69 #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) 70 typedef uint16_t TickType_t; 71 #define portMAX_DELAY ( TickType_t ) 0xffff 72 #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) 73 typedef uint32_t TickType_t; 74 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL 75 76 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do 77 * not need to be guarded with a critical section. */ 78 #define portTICK_TYPE_IS_ATOMIC 1 79 #else 80 #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. 81 #endif 82 /*-----------------------------------------------------------*/ 83 84 /** 85 * Architecture specifics. 86 */ 87 #define portARCH_NAME "Cortex-M0+" 88 #define portSTACK_GROWTH ( -1 ) 89 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) 90 #define portBYTE_ALIGNMENT 8 91 #define portNOP() 92 #define portINLINE __inline 93 #ifndef portFORCE_INLINE 94 #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) 95 #endif 96 #define portDONT_DISCARD __attribute__( ( used ) ) 97 /*-----------------------------------------------------------*/ 98 99 /** 100 * @brief Extern declarations. 101 */ 102 extern BaseType_t xPortIsInsideInterrupt( void ); 103 104 extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; 105 106 extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; 107 extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; 108 109 extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; 110 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; 111 112 #if ( configENABLE_MPU == 1 ) 113 extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; 114 extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; 115 #endif /* configENABLE_MPU */ 116 /*-----------------------------------------------------------*/ 117 118 /** 119 * @brief MPU specific constants. 120 */ 121 #if ( configENABLE_MPU == 1 ) 122 #define portUSING_MPU_WRAPPERS 1 123 #define portPRIVILEGE_BIT ( 0x80000000UL ) 124 #else 125 #define portPRIVILEGE_BIT ( 0x0UL ) 126 #endif /* configENABLE_MPU */ 127 128 /* Shareable (S), Cacheable (C) and Bufferable (B) bits for flash region. */ 129 #ifndef configS_C_B_FLASH 130 #define configS_C_B_FLASH ( 0x07UL ) 131 #endif 132 133 /* Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM region. */ 134 #ifndef configS_C_B_SRAM 135 #define configS_C_B_SRAM ( 0x07UL ) 136 #endif 137 138 /* MPU regions. */ 139 #define portPRIVILEGED_RAM_REGION ( 7UL ) 140 #define portPRIVILEGED_FLASH_REGION ( 6UL ) 141 #define portUNPRIVILEGED_FLASH_REGION ( 5UL ) 142 #define portSTACK_REGION ( 4UL ) 143 #define portFIRST_CONFIGURABLE_REGION ( 0UL ) 144 #define portLAST_CONFIGURABLE_REGION ( 3UL ) 145 #define portNUM_CONFIGURABLE_REGIONS ( 4UL ) 146 #define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1UL ) /* Plus one to make space for the stack region. */ 147 148 /* MPU region sizes. This information is encoded in the SIZE bits of the MPU 149 * Region Attribute and Size Register (RASR). */ 150 #define portMPU_REGION_SIZE_256B ( 0x07UL << 1UL ) 151 #define portMPU_REGION_SIZE_512B ( 0x08UL << 1UL ) 152 #define portMPU_REGION_SIZE_1KB ( 0x09UL << 1UL ) 153 #define portMPU_REGION_SIZE_2KB ( 0x0AUL << 1UL ) 154 #define portMPU_REGION_SIZE_4KB ( 0x0BUL << 1UL ) 155 #define portMPU_REGION_SIZE_8KB ( 0x0CUL << 1UL ) 156 #define portMPU_REGION_SIZE_16KB ( 0x0DUL << 1UL ) 157 #define portMPU_REGION_SIZE_32KB ( 0x0EUL << 1UL ) 158 #define portMPU_REGION_SIZE_64KB ( 0x0FUL << 1UL ) 159 #define portMPU_REGION_SIZE_128KB ( 0x10UL << 1UL ) 160 #define portMPU_REGION_SIZE_256KB ( 0x11UL << 1UL ) 161 #define portMPU_REGION_SIZE_512KB ( 0x12UL << 1UL ) 162 #define portMPU_REGION_SIZE_1MB ( 0x13UL << 1UL ) 163 #define portMPU_REGION_SIZE_2MB ( 0x14UL << 1UL ) 164 #define portMPU_REGION_SIZE_4MB ( 0x15UL << 1UL ) 165 #define portMPU_REGION_SIZE_8MB ( 0x16UL << 1UL ) 166 #define portMPU_REGION_SIZE_16MB ( 0x17UL << 1UL ) 167 #define portMPU_REGION_SIZE_32MB ( 0x18UL << 1UL ) 168 #define portMPU_REGION_SIZE_64MB ( 0x19UL << 1UL ) 169 #define portMPU_REGION_SIZE_128MB ( 0x1AUL << 1UL ) 170 #define portMPU_REGION_SIZE_256MB ( 0x1BUL << 1UL ) 171 #define portMPU_REGION_SIZE_512MB ( 0x1CUL << 1UL ) 172 #define portMPU_REGION_SIZE_1GB ( 0x1DUL << 1UL ) 173 #define portMPU_REGION_SIZE_2GB ( 0x1EUL << 1UL ) 174 #define portMPU_REGION_SIZE_4GB ( 0x1FUL << 1UL ) 175 176 /* MPU memory types. This information is encoded in the S ( Shareable), C 177 * (Cacheable) and B (Bufferable) bits of the MPU Region Attribute and Size 178 * Register (RASR). */ 179 #define portMPU_REGION_STRONGLY_ORDERED_SHAREABLE ( 0x0UL << 16UL ) /* S=NA, C=0, B=0. */ 180 #define portMPU_REGION_DEVICE_SHAREABLE ( 0x1UL << 16UL ) /* S=NA, C=0, B=1. */ 181 #define portMPU_REGION_NORMAL_OIWTNOWA_NONSHARED ( 0x2UL << 16UL ) /* S=0, C=1, B=0. */ 182 #define portMPU_REGION_NORMAL_OIWTNOWA_SHARED ( 0x6UL << 16UL ) /* S=1, C=1, B=0. */ 183 #define portMPU_REGION_NORMAL_OIWBNOWA_NONSHARED ( 0x3UL << 16UL ) /* S=0, C=1, B=1.*/ 184 #define portMPU_REGION_NORMAL_OIWBNOWA_SHARED ( 0x7UL << 16UL ) /* S=1, C=1, B=1.*/ 185 186 /* MPU access permissions. This information is encoded in the AP and XN bits of 187 * the MPU Region Attribute and Size Register (RASR). */ 188 #define portMPU_REGION_PRIV_NA_UNPRIV_NA ( 0x0UL << 24UL ) 189 #define portMPU_REGION_PRIV_RW_UNPRIV_NA ( 0x1UL << 24UL ) 190 #define portMPU_REGION_PRIV_RW_UNPRIV_RO ( 0x2UL << 24UL ) 191 #define portMPU_REGION_PRIV_RW_UNPRIV_RW ( 0x3UL << 24UL ) 192 #define portMPU_REGION_PRIV_RO_UNPRIV_NA ( 0x5UL << 24UL ) 193 #define portMPU_REGION_PRIV_RO_UNPRIV_RO ( 0x6UL << 24UL ) 194 #define portMPU_REGION_EXECUTE_NEVER ( 0x1UL << 28UL ) 195 196 #if ( configENABLE_MPU == 1 ) 197 198 /** 199 * @brief Settings to define an MPU region. 200 */ 201 typedef struct MPURegionSettings 202 { 203 uint32_t ulRBAR; /**< MPU Region Base Address Register (RBAR) for the region. */ 204 uint32_t ulRASR; /**< MPU Region Attribute and Size Register (RASR) for the region. */ 205 } MPURegionSettings_t; 206 207 #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) 208 209 #ifndef configSYSTEM_CALL_STACK_SIZE 210 #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. 211 #endif 212 213 /** 214 * @brief System call stack. 215 */ 216 typedef struct SYSTEM_CALL_STACK_INFO 217 { 218 uint32_t ulSystemCallStackBuffer[ configSYSTEM_CALL_STACK_SIZE ]; 219 uint32_t * pulSystemCallStack; 220 uint32_t * pulTaskStack; 221 uint32_t ulLinkRegisterAtSystemCallEntry; 222 } xSYSTEM_CALL_STACK_INFO; 223 224 #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ 225 226 /** 227 * @brief MPU settings as stored in the TCB. 228 */ 229 230 /* 231 * +----------+-----------------+---------------+-----+ 232 * | r4-r11 | r0-r3, r12, LR, | PSP, CONTROL | | 233 * | | PC, xPSR | EXC_RETURN | | 234 * +----------+-----------------+---------------+-----+ 235 * 236 * <---------><----------------><---------------><----> 237 * 8 8 3 1 238 */ 239 #define CONTEXT_SIZE 20 240 241 /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ 242 #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) 243 #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) 244 245 /* Size of an Access Control List (ACL) entry in bits. */ 246 #define portACL_ENTRY_SIZE_BITS ( 32U ) 247 248 typedef struct MPU_SETTINGS 249 { 250 MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ 251 uint32_t ulContext[ CONTEXT_SIZE ]; 252 uint32_t ulTaskFlags; 253 254 #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) 255 xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo; 256 #if ( configENABLE_ACCESS_CONTROL_LIST == 1 ) 257 uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ]; 258 #endif 259 #endif 260 } xMPU_SETTINGS; 261 262 #endif /* configENABLE_MPU == 1 */ 263 /*-----------------------------------------------------------*/ 264 265 /** 266 * @brief SVC numbers. 267 */ 268 #define portSVC_START_SCHEDULER 100 269 #define portSVC_RAISE_PRIVILEGE 101 270 #define portSVC_SYSTEM_CALL_EXIT 102 271 #define portSVC_YIELD 103 272 /*-----------------------------------------------------------*/ 273 274 /** 275 * @brief Scheduler utilities. 276 */ 277 #if ( configENABLE_MPU == 1 ) 278 #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) 279 #define portYIELD_WITHIN_API() vPortYield() 280 #else 281 #define portYIELD() vPortYield() 282 #define portYIELD_WITHIN_API() vPortYield() 283 #endif 284 285 #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) 286 #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) 287 #define portEND_SWITCHING_ISR( xSwitchRequired ) \ 288 do \ 289 { \ 290 if( xSwitchRequired ) \ 291 { \ 292 traceISR_EXIT_TO_SCHEDULER(); \ 293 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ 294 } \ 295 else \ 296 { \ 297 traceISR_EXIT(); \ 298 } \ 299 } while( 0 ) 300 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) 301 /*-----------------------------------------------------------*/ 302 303 /** 304 * @brief Critical section management. 305 */ 306 #define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMask() 307 #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMask( x ) 308 #define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) 309 #define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) 310 #define portENTER_CRITICAL() vPortEnterCritical() 311 #define portEXIT_CRITICAL() vPortExitCritical() 312 /*-----------------------------------------------------------*/ 313 314 /** 315 * @brief Tickless idle/low power functionality. 316 */ 317 #ifndef portSUPPRESS_TICKS_AND_SLEEP 318 extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); 319 #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) 320 #endif 321 /*-----------------------------------------------------------*/ 322 323 /** 324 * @brief Task function macros as described on the FreeRTOS.org website. 325 */ 326 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) 327 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) 328 /*-----------------------------------------------------------*/ 329 330 #if ( configENABLE_MPU == 1 ) 331 332 /** 333 * @brief Checks whether or not the processor is privileged. 334 * 335 * @return 1 if the processor is already privileged, 0 otherwise. 336 */ 337 #define portIS_PRIVILEGED() xIsPrivileged() 338 339 /** 340 * @brief Raise an SVC request to raise privilege. 341 * 342 * The SVC handler checks that the SVC was raised from a system call and only 343 * then it raises the privilege. If this is called from any other place, 344 * the privilege is not raised. 345 */ 346 #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); 347 348 /** 349 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL 350 * register. 351 */ 352 #define portRESET_PRIVILEGE() vResetPrivilege() 353 354 #else 355 356 #define portIS_PRIVILEGED() 357 #define portRAISE_PRIVILEGE() 358 #define portRESET_PRIVILEGE() 359 360 #endif /* configENABLE_MPU */ 361 /*-----------------------------------------------------------*/ 362 363 #if ( configENABLE_MPU == 1 ) 364 365 extern BaseType_t xPortIsTaskPrivileged( void ); 366 367 /** 368 * @brief Checks whether or not the calling task is privileged. 369 * 370 * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. 371 */ 372 #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() 373 374 #endif /* configENABLE_MPU == 1 */ 375 /*-----------------------------------------------------------*/ 376 377 /** 378 * @brief Barriers. 379 */ 380 #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) 381 /*-----------------------------------------------------------*/ 382 383 /* *INDENT-OFF* */ 384 #ifdef __cplusplus 385 } 386 #endif 387 /* *INDENT-ON* */ 388 389 #endif /* PORTMACRO_H */ 390
