xref: /FreeRTOS-Plus-TCP-v3.1.0/source/portable/NetworkInterface/STM32Fxx/stm32fxx_hal_eth.h (revision a4124602cc584fa0658448c229f48a459a84fbb1)
1 /**
2  ******************************************************************************
3  * @file    stm32fxx_hal_eth.h
4  * @author  MCD Application Team
5  * @version V1.2.2
6  * @date    14-April-2017
7  * @brief   Header file of ETH HAL module.
8  ******************************************************************************
9  * @attention
10  *
11  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12  *
13  * Redistribution and use in source and binary forms, with or without modification,
14  * are permitted provided that the following conditions are met:
15  *   1. Redistributions of source code must retain the above copyright notice,
16  *      this list of conditions and the following disclaimer.
17  *   2. Redistributions in binary form must reproduce the above copyright notice,
18  *      this list of conditions and the following disclaimer in the documentation
19  *      and/or other materials provided with the distribution.
20  *   3. Neither the name of STMicroelectronics nor the names of its contributors
21  *      may be used to endorse or promote products derived from this software
22  *      without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  ******************************************************************************
36  */
37 
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32Fxx_HAL_ETH_H
40     #define __STM32Fxx_HAL_ETH_H
41 
42 /* make sure that the original ETH headers files won't be included after this. */
43     #define __STM32F2xx_HAL_ETH_H
44     #define __STM32F4xx_HAL_ETH_H
45     #define __STM32F7xx_HAL_ETH_H
46 
47     #if defined( STM32F7xx )
48         #include "stm32f7xx_hal.h"
49     #elif defined( STM32F407xx ) || defined( STM32F417xx ) || defined( STM32F427xx ) || defined( STM32F437xx ) || defined( STM32F429xx ) || defined( STM32F439xx )
50         #include "stm32f4xx_hal.h"
51     #elif defined( STM32F2xx )
52         #include "stm32f2xx_hal.h"
53     #endif
54 
55     #ifdef __cplusplus
56         extern "C" {
57     #endif
58 
59 /** @addtogroup STM32Fxx_HAL_Driver
60  * @{
61  */
62 
63 /** @addtogroup ETH
64  * @{
65  */
66 
67 /** @addtogroup ETH_Private_Macros
68  * @{
69  */
70     #define IS_ETH_PHY_ADDRESS( ADDRESS )    ( ( ADDRESS ) <= 0x20 )
71     #define IS_ETH_AUTONEGOTIATION( CMD )          \
72     ( ( ( CMD ) == ETH_AUTONEGOTIATION_ENABLE ) || \
73       ( ( CMD ) == ETH_AUTONEGOTIATION_DISABLE ) )
74     #define IS_ETH_SPEED( SPEED )       \
75     ( ( ( SPEED ) == ETH_SPEED_10M ) || \
76       ( ( SPEED ) == ETH_SPEED_100M ) )
77     #define IS_ETH_DUPLEX_MODE( MODE )       \
78     ( ( ( MODE ) == ETH_MODE_FULLDUPLEX ) || \
79       ( ( MODE ) == ETH_MODE_HALFDUPLEX ) )
80     #define IS_ETH_DUPLEX_MODE( MODE )       \
81     ( ( ( MODE ) == ETH_MODE_FULLDUPLEX ) || \
82       ( ( MODE ) == ETH_MODE_HALFDUPLEX ) )
83     #define IS_ETH_RX_MODE( MODE )          \
84     ( ( ( MODE ) == ETH_RXPOLLING_MODE ) || \
85       ( ( MODE ) == ETH_RXINTERRUPT_MODE ) )
86     #define IS_ETH_RX_MODE( MODE )          \
87     ( ( ( MODE ) == ETH_RXPOLLING_MODE ) || \
88       ( ( MODE ) == ETH_RXINTERRUPT_MODE ) )
89     #define IS_ETH_RX_MODE( MODE )          \
90     ( ( ( MODE ) == ETH_RXPOLLING_MODE ) || \
91       ( ( MODE ) == ETH_RXINTERRUPT_MODE ) )
92     #define IS_ETH_CHECKSUM_MODE( MODE )          \
93     ( ( ( MODE ) == ETH_CHECKSUM_BY_HARDWARE ) || \
94       ( ( MODE ) == ETH_CHECKSUM_BY_SOFTWARE ) )
95     #define IS_ETH_MEDIA_INTERFACE( MODE )       \
96     ( ( ( MODE ) == ETH_MEDIA_INTERFACE_MII ) || \
97       ( ( MODE ) == ETH_MEDIA_INTERFACE_RMII ) )
98     #define IS_ETH_WATCHDOG( CMD )          \
99     ( ( ( CMD ) == ETH_WATCHDOG_ENABLE ) || \
100       ( ( CMD ) == ETH_WATCHDOG_DISABLE ) )
101     #define IS_ETH_JABBER( CMD )          \
102     ( ( ( CMD ) == ETH_JABBER_ENABLE ) || \
103       ( ( CMD ) == ETH_JABBER_DISABLE ) )
104     #define IS_ETH_INTER_FRAME_GAP( GAP )       \
105     ( ( ( GAP ) == ETH_INTERFRAMEGAP_96BIT ) || \
106       ( ( GAP ) == ETH_INTERFRAMEGAP_88BIT ) || \
107       ( ( GAP ) == ETH_INTERFRAMEGAP_80BIT ) || \
108       ( ( GAP ) == ETH_INTERFRAMEGAP_72BIT ) || \
109       ( ( GAP ) == ETH_INTERFRAMEGAP_64BIT ) || \
110       ( ( GAP ) == ETH_INTERFRAMEGAP_56BIT ) || \
111       ( ( GAP ) == ETH_INTERFRAMEGAP_48BIT ) || \
112       ( ( GAP ) == ETH_INTERFRAMEGAP_40BIT ) )
113     #define IS_ETH_CARRIER_SENSE( CMD )         \
114     ( ( ( CMD ) == ETH_CARRIERSENCE_ENABLE ) || \
115       ( ( CMD ) == ETH_CARRIERSENCE_DISABLE ) )
116     #define IS_ETH_RECEIVE_OWN( CMD )         \
117     ( ( ( CMD ) == ETH_RECEIVEOWN_ENABLE ) || \
118       ( ( CMD ) == ETH_RECEIVEOWN_DISABLE ) )
119     #define IS_ETH_LOOPBACK_MODE( CMD )         \
120     ( ( ( CMD ) == ETH_LOOPBACKMODE_ENABLE ) || \
121       ( ( CMD ) == ETH_LOOPBACKMODE_DISABLE ) )
122     #define IS_ETH_CHECKSUM_OFFLOAD( CMD )         \
123     ( ( ( CMD ) == ETH_CHECKSUMOFFLAOD_ENABLE ) || \
124       ( ( CMD ) == ETH_CHECKSUMOFFLAOD_DISABLE ) )
125     #define IS_ETH_RETRY_TRANSMISSION( CMD )         \
126     ( ( ( CMD ) == ETH_RETRYTRANSMISSION_ENABLE ) || \
127       ( ( CMD ) == ETH_RETRYTRANSMISSION_DISABLE ) )
128     #define IS_ETH_AUTOMATIC_PADCRC_STRIP( CMD )        \
129     ( ( ( CMD ) == ETH_AUTOMATICPADCRCSTRIP_ENABLE ) || \
130       ( ( CMD ) == ETH_AUTOMATICPADCRCSTRIP_DISABLE ) )
131     #define IS_ETH_BACKOFF_LIMIT( LIMIT )     \
132     ( ( ( LIMIT ) == ETH_BACKOFFLIMIT_10 ) || \
133       ( ( LIMIT ) == ETH_BACKOFFLIMIT_8 ) ||  \
134       ( ( LIMIT ) == ETH_BACKOFFLIMIT_4 ) ||  \
135       ( ( LIMIT ) == ETH_BACKOFFLIMIT_1 ) )
136     #define IS_ETH_DEFERRAL_CHECK( CMD )          \
137     ( ( ( CMD ) == ETH_DEFFERRALCHECK_ENABLE ) || \
138       ( ( CMD ) == ETH_DEFFERRALCHECK_DISABLE ) )
139     #define IS_ETH_RECEIVE_ALL( CMD )         \
140     ( ( ( CMD ) == ETH_RECEIVEALL_ENABLE ) || \
141       ( ( CMD ) == ETH_RECEIVEAll_DISABLE ) )
142     #define IS_ETH_SOURCE_ADDR_FILTER( CMD )                \
143     ( ( ( CMD ) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE ) ||  \
144       ( ( CMD ) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE ) || \
145       ( ( CMD ) == ETH_SOURCEADDRFILTER_DISABLE ) )
146     #define IS_ETH_CONTROL_FRAMES( PASS )                 \
147     ( ( ( PASS ) == ETH_PASSCONTROLFRAMES_BLOCKALL ) ||   \
148       ( ( PASS ) == ETH_PASSCONTROLFRAMES_FORWARDALL ) || \
149       ( ( PASS ) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ) )
150     #define IS_ETH_BROADCAST_FRAMES_RECEPTION( CMD )        \
151     ( ( ( CMD ) == ETH_BROADCASTFRAMESRECEPTION_ENABLE ) || \
152       ( ( CMD ) == ETH_BROADCASTFRAMESRECEPTION_DISABLE ) )
153     #define IS_ETH_DESTINATION_ADDR_FILTER( FILTER )        \
154     ( ( ( FILTER ) == ETH_DESTINATIONADDRFILTER_NORMAL ) || \
155       ( ( FILTER ) == ETH_DESTINATIONADDRFILTER_INVERSE ) )
156     #define IS_ETH_PROMISCUOUS_MODE( CMD )          \
157     ( ( ( CMD ) == ETH_PROMISCUOUS_MODE_ENABLE ) || \
158       ( ( CMD ) == ETH_PROMISCUOUS_MODE_DISABLE ) )
159     #define IS_ETH_MULTICAST_FRAMES_FILTER( FILTER )                  \
160     ( ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ) || \
161       ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_HASHTABLE ) ||        \
162       ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_PERFECT ) ||          \
163       ( ( FILTER ) == ETH_MULTICASTFRAMESFILTER_NONE ) )
164     #define IS_ETH_UNICAST_FRAMES_FILTER( FILTER )                  \
165     ( ( ( FILTER ) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ) || \
166       ( ( FILTER ) == ETH_UNICASTFRAMESFILTER_HASHTABLE ) ||        \
167       ( ( FILTER ) == ETH_UNICASTFRAMESFILTER_PERFECT ) )
168     #define IS_ETH_PAUSE_TIME( TIME )    ( ( TIME ) <= 0xFFFF )
169     #define IS_ETH_ZEROQUANTA_PAUSE( CMD )         \
170     ( ( ( CMD ) == ETH_ZEROQUANTAPAUSE_ENABLE ) || \
171       ( ( CMD ) == ETH_ZEROQUANTAPAUSE_DISABLE ) )
172     #define IS_ETH_PAUSE_LOW_THRESHOLD( THRESHOLD )          \
173     ( ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS4 ) ||   \
174       ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS28 ) ||  \
175       ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS144 ) || \
176       ( ( THRESHOLD ) == ETH_PAUSELOWTHRESHOLD_MINUS256 ) )
177     #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT( CMD )       \
178     ( ( ( CMD ) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ) || \
179       ( ( CMD ) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ) )
180     #define IS_ETH_RECEIVE_FLOWCONTROL( CMD )         \
181     ( ( ( CMD ) == ETH_RECEIVEFLOWCONTROL_ENABLE ) || \
182       ( ( CMD ) == ETH_RECEIVEFLOWCONTROL_DISABLE ) )
183     #define IS_ETH_TRANSMIT_FLOWCONTROL( CMD )         \
184     ( ( ( CMD ) == ETH_TRANSMITFLOWCONTROL_ENABLE ) || \
185       ( ( CMD ) == ETH_TRANSMITFLOWCONTROL_DISABLE ) )
186     #define IS_ETH_VLAN_TAG_COMPARISON( COMPARISON )       \
187     ( ( ( COMPARISON ) == ETH_VLANTAGCOMPARISON_12BIT ) || \
188       ( ( COMPARISON ) == ETH_VLANTAGCOMPARISON_16BIT ) )
189     #define IS_ETH_VLAN_TAG_IDENTIFIER( IDENTIFIER )    ( ( IDENTIFIER ) <= 0xFFFF )
190     #define IS_ETH_MAC_ADDRESS0123( ADDRESS ) \
191     ( ( ( ADDRESS ) == ETH_MAC_ADDRESS0 ) ||  \
192       ( ( ADDRESS ) == ETH_MAC_ADDRESS1 ) ||  \
193       ( ( ADDRESS ) == ETH_MAC_ADDRESS2 ) ||  \
194       ( ( ADDRESS ) == ETH_MAC_ADDRESS3 ) )
195     #define IS_ETH_MAC_ADDRESS123( ADDRESS ) \
196     ( ( ( ADDRESS ) == ETH_MAC_ADDRESS1 ) || \
197       ( ( ADDRESS ) == ETH_MAC_ADDRESS2 ) || \
198       ( ( ADDRESS ) == ETH_MAC_ADDRESS3 ) )
199     #define IS_ETH_MAC_ADDRESS_FILTER( FILTER )     \
200     ( ( ( FILTER ) == ETH_MAC_ADDRESSFILTER_SA ) || \
201       ( ( FILTER ) == ETH_MAC_ADDRESSFILTER_DA ) )
202     #define IS_ETH_MAC_ADDRESS_MASK( MASK )        \
203     ( ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE6 ) || \
204       ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE5 ) || \
205       ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE4 ) || \
206       ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE3 ) || \
207       ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE2 ) || \
208       ( ( MASK ) == ETH_MAC_ADDRESSMASK_BYTE1 ) )
209     #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME( CMD )            \
210     ( ( ( CMD ) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ) || \
211       ( ( CMD ) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ) )
212     #define IS_ETH_RECEIVE_STORE_FORWARD( CMD )        \
213     ( ( ( CMD ) == ETH_RECEIVESTOREFORWARD_ENABLE ) || \
214       ( ( CMD ) == ETH_RECEIVESTOREFORWARD_DISABLE ) )
215     #define IS_ETH_FLUSH_RECEIVE_FRAME( CMD )         \
216     ( ( ( CMD ) == ETH_FLUSHRECEIVEDFRAME_ENABLE ) || \
217       ( ( CMD ) == ETH_FLUSHRECEIVEDFRAME_DISABLE ) )
218     #define IS_ETH_TRANSMIT_STORE_FORWARD( CMD )        \
219     ( ( ( CMD ) == ETH_TRANSMITSTOREFORWARD_ENABLE ) || \
220       ( ( CMD ) == ETH_TRANSMITSTOREFORWARD_DISABLE ) )
221     #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL( THRESHOLD )          \
222     ( ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ) ||  \
223       ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ) || \
224       ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ) || \
225       ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ) || \
226       ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ) ||  \
227       ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ) ||  \
228       ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ) ||  \
229       ( ( THRESHOLD ) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ) )
230     #define IS_ETH_FORWARD_ERROR_FRAMES( CMD )        \
231     ( ( ( CMD ) == ETH_FORWARDERRORFRAMES_ENABLE ) || \
232       ( ( CMD ) == ETH_FORWARDERRORFRAMES_DISABLE ) )
233     #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES( CMD )       \
234     ( ( ( CMD ) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ) || \
235       ( ( CMD ) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ) )
236     #define IS_ETH_RECEIVE_THRESHOLD_CONTROL( THRESHOLD )          \
237     ( ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ) || \
238       ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ) || \
239       ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ) || \
240       ( ( THRESHOLD ) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ) )
241     #define IS_ETH_SECOND_FRAME_OPERATE( CMD )         \
242     ( ( ( CMD ) == ETH_SECONDFRAMEOPERARTE_ENABLE ) || \
243       ( ( CMD ) == ETH_SECONDFRAMEOPERARTE_DISABLE ) )
244     #define IS_ETH_ADDRESS_ALIGNED_BEATS( CMD )        \
245     ( ( ( CMD ) == ETH_ADDRESSALIGNEDBEATS_ENABLE ) || \
246       ( ( CMD ) == ETH_ADDRESSALIGNEDBEATS_DISABLE ) )
247     #define IS_ETH_FIXED_BURST( CMD )         \
248     ( ( ( CMD ) == ETH_FIXEDBURST_ENABLE ) || \
249       ( ( CMD ) == ETH_FIXEDBURST_DISABLE ) )
250     #define IS_ETH_RXDMA_BURST_LENGTH( LENGTH )              \
251     ( ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_1BEAT ) ||        \
252       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_2BEAT ) ||        \
253       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4BEAT ) ||        \
254       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_8BEAT ) ||        \
255       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_16BEAT ) ||       \
256       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_32BEAT ) ||       \
257       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ) ||  \
258       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ) ||  \
259       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ) || \
260       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ) || \
261       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ) || \
262       ( ( LENGTH ) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ) )
263     #define IS_ETH_TXDMA_BURST_LENGTH( LENGTH )              \
264     ( ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_1BEAT ) ||        \
265       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_2BEAT ) ||        \
266       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4BEAT ) ||        \
267       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_8BEAT ) ||        \
268       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_16BEAT ) ||       \
269       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_32BEAT ) ||       \
270       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ) ||  \
271       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ) ||  \
272       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ) || \
273       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ) || \
274       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ) || \
275       ( ( LENGTH ) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ) )
276     #define IS_ETH_DMA_DESC_SKIP_LENGTH( LENGTH )    ( ( LENGTH ) <= 0x1F )
277     #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX( RATIO )      \
278     ( ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ) || \
279       ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ) || \
280       ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ) || \
281       ( ( RATIO ) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ) || \
282       ( ( RATIO ) == ETH_DMAARBITRATION_RXPRIORTX ) )
283     #define IS_ETH_DMATXDESC_GET_FLAG( FLAG ) \
284     ( ( ( FLAG ) == ETH_DMATXDESC_OWN ) ||    \
285       ( ( FLAG ) == ETH_DMATXDESC_IC ) ||     \
286       ( ( FLAG ) == ETH_DMATXDESC_LS ) ||     \
287       ( ( FLAG ) == ETH_DMATXDESC_FS ) ||     \
288       ( ( FLAG ) == ETH_DMATXDESC_DC ) ||     \
289       ( ( FLAG ) == ETH_DMATXDESC_DP ) ||     \
290       ( ( FLAG ) == ETH_DMATXDESC_TTSE ) ||   \
291       ( ( FLAG ) == ETH_DMATXDESC_TER ) ||    \
292       ( ( FLAG ) == ETH_DMATXDESC_TCH ) ||    \
293       ( ( FLAG ) == ETH_DMATXDESC_TTSS ) ||   \
294       ( ( FLAG ) == ETH_DMATXDESC_IHE ) ||    \
295       ( ( FLAG ) == ETH_DMATXDESC_ES ) ||     \
296       ( ( FLAG ) == ETH_DMATXDESC_JT ) ||     \
297       ( ( FLAG ) == ETH_DMATXDESC_FF ) ||     \
298       ( ( FLAG ) == ETH_DMATXDESC_PCE ) ||    \
299       ( ( FLAG ) == ETH_DMATXDESC_LCA ) ||    \
300       ( ( FLAG ) == ETH_DMATXDESC_NC ) ||     \
301       ( ( FLAG ) == ETH_DMATXDESC_LCO ) ||    \
302       ( ( FLAG ) == ETH_DMATXDESC_EC ) ||     \
303       ( ( FLAG ) == ETH_DMATXDESC_VF ) ||     \
304       ( ( FLAG ) == ETH_DMATXDESC_CC ) ||     \
305       ( ( FLAG ) == ETH_DMATXDESC_ED ) ||     \
306       ( ( FLAG ) == ETH_DMATXDESC_UF ) ||     \
307       ( ( FLAG ) == ETH_DMATXDESC_DB ) )
308     #define IS_ETH_DMA_TXDESC_SEGMENT( SEGMENT )       \
309     ( ( ( SEGMENT ) == ETH_DMATXDESC_LASTSEGMENTS ) || \
310       ( ( SEGMENT ) == ETH_DMATXDESC_FIRSTSEGMENT ) )
311     #define IS_ETH_DMA_TXDESC_CHECKSUM( CHECKSUM )                   \
312     ( ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMBYPASS ) ||            \
313       ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMIPV4HEADER ) ||        \
314       ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ) || \
315       ( ( CHECKSUM ) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ) )
316     #define IS_ETH_DMATXDESC_BUFFER_SIZE( SIZE )    ( ( SIZE ) <= 0x1FFF )
317     #define IS_ETH_DMARXDESC_GET_FLAG( FLAG )  \
318     ( ( ( FLAG ) == ETH_DMARXDESC_OWN ) ||     \
319       ( ( FLAG ) == ETH_DMARXDESC_AFM ) ||     \
320       ( ( FLAG ) == ETH_DMARXDESC_ES ) ||      \
321       ( ( FLAG ) == ETH_DMARXDESC_DE ) ||      \
322       ( ( FLAG ) == ETH_DMARXDESC_SAF ) ||     \
323       ( ( FLAG ) == ETH_DMARXDESC_LE ) ||      \
324       ( ( FLAG ) == ETH_DMARXDESC_OE ) ||      \
325       ( ( FLAG ) == ETH_DMARXDESC_VLAN ) ||    \
326       ( ( FLAG ) == ETH_DMARXDESC_FS ) ||      \
327       ( ( FLAG ) == ETH_DMARXDESC_LS ) ||      \
328       ( ( FLAG ) == ETH_DMARXDESC_IPV4HCE ) || \
329       ( ( FLAG ) == ETH_DMARXDESC_LC ) ||      \
330       ( ( FLAG ) == ETH_DMARXDESC_FT ) ||      \
331       ( ( FLAG ) == ETH_DMARXDESC_RWT ) ||     \
332       ( ( FLAG ) == ETH_DMARXDESC_RE ) ||      \
333       ( ( FLAG ) == ETH_DMARXDESC_DBE ) ||     \
334       ( ( FLAG ) == ETH_DMARXDESC_CE ) ||      \
335       ( ( FLAG ) == ETH_DMARXDESC_MAMPCE ) )
336     #define IS_ETH_DMA_RXDESC_BUFFER( BUFFER )   \
337     ( ( ( BUFFER ) == ETH_DMARXDESC_BUFFER1 ) || \
338       ( ( BUFFER ) == ETH_DMARXDESC_BUFFER2 ) )
339     #define IS_ETH_PMT_GET_FLAG( FLAG )    \
340     ( ( ( FLAG ) == ETH_PMT_FLAG_WUFR ) || \
341       ( ( FLAG ) == ETH_PMT_FLAG_MPR ) )
342     #define IS_ETH_DMA_FLAG( FLAG )    ( ( ( ( FLAG ) &( uint32_t ) 0xC7FE1800 ) == 0x00 ) && ( ( FLAG ) != 0x00 ) )
343     #define IS_ETH_DMA_GET_FLAG( FLAG )                                                          \
344     ( ( ( FLAG ) == ETH_DMA_FLAG_TST ) || ( ( FLAG ) == ETH_DMA_FLAG_PMT ) ||                    \
345       ( ( FLAG ) == ETH_DMA_FLAG_MMC ) || ( ( FLAG ) == ETH_DMA_FLAG_DATATRANSFERERROR ) ||      \
346       ( ( FLAG ) == ETH_DMA_FLAG_READWRITEERROR ) || ( ( FLAG ) == ETH_DMA_FLAG_ACCESSERROR ) || \
347       ( ( FLAG ) == ETH_DMA_FLAG_NIS ) || ( ( FLAG ) == ETH_DMA_FLAG_AIS ) ||                    \
348       ( ( FLAG ) == ETH_DMA_FLAG_ER ) || ( ( FLAG ) == ETH_DMA_FLAG_FBE ) ||                     \
349       ( ( FLAG ) == ETH_DMA_FLAG_ET ) || ( ( FLAG ) == ETH_DMA_FLAG_RWT ) ||                     \
350       ( ( FLAG ) == ETH_DMA_FLAG_RPS ) || ( ( FLAG ) == ETH_DMA_FLAG_RBU ) ||                    \
351       ( ( FLAG ) == ETH_DMA_FLAG_R ) || ( ( FLAG ) == ETH_DMA_FLAG_TU ) ||                       \
352       ( ( FLAG ) == ETH_DMA_FLAG_RO ) || ( ( FLAG ) == ETH_DMA_FLAG_TJT ) ||                     \
353       ( ( FLAG ) == ETH_DMA_FLAG_TBU ) || ( ( FLAG ) == ETH_DMA_FLAG_TPS ) ||                    \
354       ( ( FLAG ) == ETH_DMA_FLAG_T ) )
355     #define IS_ETH_MAC_IT( IT )        ( ( ( ( IT ) &( uint32_t ) 0xFFFFFDF1 ) == 0x00 ) && ( ( IT ) != 0x00 ) )
356     #define IS_ETH_MAC_GET_IT( IT )                                    \
357     ( ( ( IT ) == ETH_MAC_IT_TST ) || ( ( IT ) == ETH_MAC_IT_MMCT ) || \
358       ( ( IT ) == ETH_MAC_IT_MMCR ) || ( ( IT ) == ETH_MAC_IT_MMC ) || \
359       ( ( IT ) == ETH_MAC_IT_PMT ) )
360     #define IS_ETH_MAC_GET_FLAG( FLAG )                                        \
361     ( ( ( FLAG ) == ETH_MAC_FLAG_TST ) || ( ( FLAG ) == ETH_MAC_FLAG_MMCT ) || \
362       ( ( FLAG ) == ETH_MAC_FLAG_MMCR ) || ( ( FLAG ) == ETH_MAC_FLAG_MMC ) || \
363       ( ( FLAG ) == ETH_MAC_FLAG_PMT ) )
364     #define IS_ETH_DMA_IT( IT )        ( ( ( ( IT ) &( uint32_t ) 0xC7FE1800 ) == 0x00 ) && ( ( IT ) != 0x00 ) )
365     #define IS_ETH_DMA_GET_IT( IT )                                   \
366     ( ( ( IT ) == ETH_DMA_IT_TST ) || ( ( IT ) == ETH_DMA_IT_PMT ) || \
367       ( ( IT ) == ETH_DMA_IT_MMC ) || ( ( IT ) == ETH_DMA_IT_NIS ) || \
368       ( ( IT ) == ETH_DMA_IT_AIS ) || ( ( IT ) == ETH_DMA_IT_ER ) ||  \
369       ( ( IT ) == ETH_DMA_IT_FBE ) || ( ( IT ) == ETH_DMA_IT_ET ) ||  \
370       ( ( IT ) == ETH_DMA_IT_RWT ) || ( ( IT ) == ETH_DMA_IT_RPS ) || \
371       ( ( IT ) == ETH_DMA_IT_RBU ) || ( ( IT ) == ETH_DMA_IT_R ) ||   \
372       ( ( IT ) == ETH_DMA_IT_TU ) || ( ( IT ) == ETH_DMA_IT_RO ) ||   \
373       ( ( IT ) == ETH_DMA_IT_TJT ) || ( ( IT ) == ETH_DMA_IT_TBU ) || \
374       ( ( IT ) == ETH_DMA_IT_TPS ) || ( ( IT ) == ETH_DMA_IT_T ) )
375     #define IS_ETH_DMA_GET_OVERFLOW( OVERFLOW )             \
376     ( ( ( OVERFLOW ) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER ) || \
377       ( ( OVERFLOW ) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ) )
378     #define IS_ETH_MMC_IT( IT )                                                                                 \
379     ( ( ( ( ( IT ) &( uint32_t ) 0xFFDF3FFF ) == 0x00 ) || ( ( ( IT ) &( uint32_t ) 0xEFFDFF9F ) == 0x00 ) ) && \
380       ( ( IT ) != 0x00 ) )
381     #define IS_ETH_MMC_GET_IT( IT )                                      \
382     ( ( ( IT ) == ETH_MMC_IT_TGF ) || ( ( IT ) == ETH_MMC_IT_TGFMSC ) || \
383       ( ( IT ) == ETH_MMC_IT_TGFSC ) || ( ( IT ) == ETH_MMC_IT_RGUF ) || \
384       ( ( IT ) == ETH_MMC_IT_RFAE ) || ( ( IT ) == ETH_MMC_IT_RFCE ) )
385     #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT( CMD )     \
386     ( ( ( CMD ) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE ) || \
387       ( ( CMD ) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE ) )
388 
389 
390 /**
391  * @}
392  */
393 
394 /** @addtogroup ETH_Private_Defines
395  * @{
396  */
397 /* Delay to wait when writing to some Ethernet registers */
398     #define ETH_REG_WRITE_DELAY                               ( ( uint32_t ) 0x00000001U )
399 
400 /* Ethernet Errors */
401     #define  ETH_SUCCESS                                      ( ( uint32_t ) 0U )
402     #define  ETH_ERROR                                        ( ( uint32_t ) 1U )
403 
404 /* Ethernet DMA Tx descriptors Collision Count Shift */
405     #define  ETH_DMATXDESC_COLLISION_COUNTSHIFT               ( ( uint32_t ) 3U )
406 
407 /* Ethernet DMA Tx descriptors Buffer2 Size Shift */
408     #define  ETH_DMATXDESC_BUFFER2_SIZESHIFT                  ( ( uint32_t ) 16U )
409 
410 /* Ethernet DMA Rx descriptors Frame Length Shift */
411     #define  ETH_DMARXDESC_FRAME_LENGTHSHIFT                  ( ( uint32_t ) 16U )
412 
413 /* Ethernet DMA Rx descriptors Buffer2 Size Shift */
414     #define  ETH_DMARXDESC_BUFFER2_SIZESHIFT                  ( ( uint32_t ) 16U )
415 
416 /* Ethernet DMA Rx descriptors Frame length Shift */
417     #define  ETH_DMARXDESC_FRAMELENGTHSHIFT                   ( ( uint32_t ) 16U )
418 
419 /* Ethernet MAC address offsets */
420     #define ETH_MAC_ADDR_HBASE                                ( uint32_t ) ( ETH_MAC_BASE + ( uint32_t ) 0x40U ) /* Ethernet MAC address high offset */
421     #define ETH_MAC_ADDR_LBASE                                ( uint32_t ) ( ETH_MAC_BASE + ( uint32_t ) 0x44U ) /* Ethernet MAC address low offset */
422 
423 /* Ethernet MACMIIAR register Mask */
424     #define ETH_MACMIIAR_CR_MASK                              ( ( uint32_t ) 0xFFFFFFE3U )
425 
426 /* Ethernet MACCR register Mask */
427     #define ETH_MACCR_CLEAR_MASK                              ( ( uint32_t ) 0xFF20810FU )
428 
429 /* Ethernet MACFCR register Mask */
430     #define ETH_MACFCR_CLEAR_MASK                             ( ( uint32_t ) 0x0000FF41U )
431 
432 /* Ethernet DMAOMR register Mask */
433     #define ETH_DMAOMR_CLEAR_MASK                             ( ( uint32_t ) 0xF8DE3F23U )
434 
435 /* Ethernet Remote Wake-up frame register length */
436     #define ETH_WAKEUP_REGISTER_LENGTH                        8U
437 
438 /* Ethernet Missed frames counter Shift */
439     #define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT    17U
440 
441 /**
442  * @}
443  */
444 
445     #ifdef _lint
446         #ifdef __IO
447             #undef __IO
448         #endif
449         #define __IO
450 
451         #ifdef ETH_TypeDef
452             #undef ETH_TypeDef
453         #endif
454         #define ETH_TypeDef    void
455 
456         #ifdef HAL_LockTypeDef
457             #undef HAL_LockTypeDef
458         #endif
459         #define HAL_LockTypeDef    unsigned
460 
461         #ifdef ETH_RX_BUF_SIZE
462             #undef ETH_RX_BUF_SIZE
463         #endif
464         #define ETH_RX_BUF_SIZE    1536
465 
466         #ifdef ETH_TX_BUF_SIZE
467             #undef ETH_TX_BUF_SIZE
468         #endif
469         #define ETH_TX_BUF_SIZE    1536
470     #endif /* ifdef _lint */
471 
472 /* Exported types ------------------------------------------------------------*/
473 
474 /** @defgroup ETH_Exported_Types ETH Exported Types
475  * @{
476  */
477 
478 /**
479  * @brief  HAL State structures definition
480  */
481     typedef enum
482     {
483         HAL_ETH_STATE_RESET = 0x00U,      /*!< Peripheral not yet Initialized or disabled         */
484         HAL_ETH_STATE_READY = 0x01U,      /*!< Peripheral Initialized and ready for use           */
485         HAL_ETH_STATE_BUSY = 0x02U,       /*!< an internal process is ongoing                     */
486         HAL_ETH_STATE_BUSY_TX = 0x12U,    /*!< Data Transmission process is ongoing               */
487         HAL_ETH_STATE_BUSY_RX = 0x22U,    /*!< Data Reception process is ongoing                  */
488         HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
489         HAL_ETH_STATE_BUSY_WR = 0x42U,    /*!< Write process is ongoing                           */
490         HAL_ETH_STATE_BUSY_RD = 0x82U,    /*!< Read process is ongoing                            */
491         HAL_ETH_STATE_TIMEOUT = 0x03U,    /*!< Timeout state                                      */
492         HAL_ETH_STATE_ERROR = 0x04U       /*!< Reception process is ongoing                       */
493     } HAL_ETH_StateTypeDef;
494 
495 /**
496  * @brief  ETH Init Structure definition
497  */
498 
499     typedef struct
500     {
501         uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
502                                    *       The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
503                                    *       and the mode (half/full-duplex).
504                                    *       This parameter can be a value of @ref ETH_AutoNegotiation */
505 
506         uint32_t Speed;           /*!< Sets the Ethernet speed: 10/100 Mbps.
507                                    *       This parameter can be a value of @ref ETH_Speed */
508 
509         uint32_t DuplexMode;      /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
510                                    *       This parameter can be a value of @ref ETH_Duplex_Mode */
511 
512         uint16_t PhyAddress;      /*!< Ethernet PHY address.
513                                    *       This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
514 
515         uint8_t * MACAddr;        /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
516 
517         uint32_t RxMode;          /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
518                                    *       This parameter can be a value of @ref ETH_Rx_Mode */
519 
520         uint32_t ChecksumMode;    /*!< Selects if the checksum is check by hardware or by software.
521                                    *     This parameter can be a value of @ref ETH_Checksum_Mode */
522 
523         uint32_t MediaInterface;  /*!< Selects the media-independent interface or the reduced media-independent interface.
524                                    *     This parameter can be a value of @ref ETH_Media_Interface */
525     } ETH_InitTypeDef;
526 
527 
528 /**
529  * @brief  ETH MAC Configuration Structure definition
530  */
531 
532     typedef struct
533     {
534         uint32_t Watchdog;                 /*!< Selects or not the Watchdog timer
535                                             *       When enabled, the MAC allows no more then 2048 bytes to be received.
536                                             *       When disabled, the MAC can receive up to 16384 bytes.
537                                             *       This parameter can be a value of @ref ETH_Watchdog */
538 
539         uint32_t Jabber;                   /*!< Selects or not Jabber timer
540                                             *       When enabled, the MAC allows no more then 2048 bytes to be sent.
541                                             *       When disabled, the MAC can send up to 16384 bytes.
542                                             *       This parameter can be a value of @ref ETH_Jabber */
543 
544         uint32_t InterFrameGap;            /*!< Selects the minimum IFG between frames during transmission.
545                                             *       This parameter can be a value of @ref ETH_Inter_Frame_Gap */
546 
547         uint32_t CarrierSense;             /*!< Selects or not the Carrier Sense.
548                                             *       This parameter can be a value of @ref ETH_Carrier_Sense */
549 
550         uint32_t ReceiveOwn;               /*!< Selects or not the ReceiveOwn,
551                                             *       ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
552                                             *       in Half-Duplex mode.
553                                             *       This parameter can be a value of @ref ETH_Receive_Own */
554 
555         uint32_t LoopbackMode;             /*!< Selects or not the internal MAC MII Loopback mode.
556                                             *       This parameter can be a value of @ref ETH_Loop_Back_Mode */
557 
558         uint32_t ChecksumOffload;          /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
559                                             *       This parameter can be a value of @ref ETH_Checksum_Offload */
560 
561         uint32_t RetryTransmission;        /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
562                                             *       when a collision occurs (Half-Duplex mode).
563                                             *       This parameter can be a value of @ref ETH_Retry_Transmission */
564 
565         uint32_t AutomaticPadCRCStrip;     /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
566                                             *       This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
567 
568         uint32_t BackOffLimit;             /*!< Selects the BackOff limit value.
569                                             *       This parameter can be a value of @ref ETH_Back_Off_Limit */
570 
571         uint32_t DeferralCheck;            /*!< Selects or not the deferral check function (Half-Duplex mode).
572                                            *       This parameter can be a value of @ref ETH_Deferral_Check */
573 
574         uint32_t ReceiveAll;               /*!< Selects or not all frames reception by the MAC (No filtering).
575                                             *       This parameter can be a value of @ref ETH_Receive_All */
576 
577         uint32_t SourceAddrFilter;         /*!< Selects the Source Address Filter mode.
578                                             *       This parameter can be a value of @ref ETH_Source_Addr_Filter */
579 
580         uint32_t PassControlFrames;        /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
581                                             *       This parameter can be a value of @ref ETH_Pass_Control_Frames */
582 
583         uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
584                                             *       This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
585 
586         uint32_t DestinationAddrFilter;    /*!< Sets the destination filter mode for both unicast and multicast frames.
587                                            *       This parameter can be a value of @ref ETH_Destination_Addr_Filter */
588 
589         uint32_t PromiscuousMode;          /*!< Selects or not the Promiscuous Mode
590                                             *       This parameter can be a value of @ref ETH_Promiscuous_Mode */
591 
592         uint32_t MulticastFramesFilter;    /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
593                                             *       This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
594 
595         uint32_t UnicastFramesFilter;      /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
596                                             *       This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
597 
598         uint32_t HashTableHigh;            /*!< This field holds the higher 32 bits of Hash table.
599                                             *       This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
600 
601         uint32_t HashTableLow;             /*!< This field holds the lower 32 bits of Hash table.
602                                             *       This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */
603 
604         uint32_t PauseTime;                /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
605                                             *       This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
606 
607         uint32_t ZeroQuantaPause;          /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
608                                             *       This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
609 
610         uint32_t PauseLowThreshold;        /*!< This field configures the threshold of the PAUSE to be checked for
611                                             *       automatic retransmission of PAUSE Frame.
612                                             *       This parameter can be a value of @ref ETH_Pause_Low_Threshold */
613 
614         uint32_t UnicastPauseFrameDetect;  /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
615                                             *       unicast address and unique multicast address).
616                                             *       This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
617 
618         uint32_t ReceiveFlowControl;       /*!< Enables or disables the MAC to decode the received Pause frame and
619                                             *       disable its transmitter for a specified time (Pause Time)
620                                             *       This parameter can be a value of @ref ETH_Receive_Flow_Control */
621 
622         uint32_t TransmitFlowControl;      /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
623                                             *       or the MAC back-pressure operation (Half-Duplex mode)
624                                             *       This parameter can be a value of @ref ETH_Transmit_Flow_Control */
625 
626         uint32_t VLANTagComparison;        /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
627                                             *       comparison and filtering.
628                                             *       This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
629 
630         uint32_t VLANTagIdentifier;        /*!< Holds the VLAN tag identifier for receive frames */
631     } ETH_MACInitTypeDef;
632 
633 
634 /**
635  * @brief  ETH DMA Configuration Structure definition
636  */
637 
638     typedef struct
639     {
640         uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
641                                                *       This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
642 
643         uint32_t ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.
644                                                *       This parameter can be a value of @ref ETH_Receive_Store_Forward */
645 
646         uint32_t FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.
647                                                *       This parameter can be a value of @ref ETH_Flush_Received_Frame */
648 
649         uint32_t TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.
650                                                *       This parameter can be a value of @ref ETH_Transmit_Store_Forward */
651 
652         uint32_t TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
653                                                *       This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
654 
655         uint32_t ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.
656                                                *       This parameter can be a value of @ref ETH_Forward_Error_Frames */
657 
658         uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
659                                                *       and length less than 64 bytes) including pad-bytes and CRC)
660                                                *       This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
661 
662         uint32_t ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.
663                                                *       This parameter can be a value of @ref ETH_Receive_Threshold_Control */
664 
665         uint32_t SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
666                                                *       frame of Transmit data even before obtaining the status for the first frame.
667                                                *       This parameter can be a value of @ref ETH_Second_Frame_Operate */
668 
669         uint32_t AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.
670                                                *       This parameter can be a value of @ref ETH_Address_Aligned_Beats */
671 
672         uint32_t FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.
673                                                *       This parameter can be a value of @ref ETH_Fixed_Burst */
674 
675         uint32_t RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
676                                                *       This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
677 
678         uint32_t TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
679                                                *       This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
680 
681         uint32_t EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format.
682                                                *       This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
683 
684         uint32_t DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
685                                                *       This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
686 
687         uint32_t DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.
688                                                *       This parameter can be a value of @ref ETH_DMA_Arbitration */
689     } ETH_DMAInitTypeDef;
690 
691 
692 /**
693  * @brief  ETH DMA Descriptors data structure definition
694  */
695 
696     typedef struct
697     {
698         __IO uint32_t Status;         /*!< Status */
699 
700         uint32_t ControlBufferSize;   /*!< Control and Buffer1, Buffer2 lengths */
701 
702         uint32_t Buffer1Addr;         /*!< Buffer1 address pointer */
703 
704         uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
705 
706         /*!< Enhanced Ethernet DMA PTP Descriptors */
707         uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
708 
709         uint32_t Reserved1;      /*!< Reserved */
710 
711         uint32_t TimeStampLow;   /*!< Time Stamp Low value for transmit and receive */
712 
713         uint32_t TimeStampHigh;  /*!< Time Stamp High value for transmit and receive */
714     } ETH_DMADescTypeDef;
715 
716 
717 /**
718  * @brief  Received Frame Informations structure definition
719  */
720     typedef struct
721     {
722         ETH_DMADescTypeDef * FSRxDesc; /*!< First Segment Rx Desc */
723 
724         ETH_DMADescTypeDef * LSRxDesc; /*!< Last Segment Rx Desc */
725 
726         uint32_t SegCount;             /*!< Segment count */
727 
728         uint32_t length;               /*!< Frame length */
729 
730         uint32_t buffer;               /*!< Frame buffer */
731     } ETH_DMARxFrameInfos;
732 
733 
734 /**
735  * @brief  ETH Handle Structure definition
736  */
737 
738     typedef struct
739     {
740         ETH_TypeDef * Instance;           /*!< Register base address       */
741 
742         ETH_InitTypeDef Init;             /*!< Ethernet Init Configuration */
743 
744         uint32_t LinkStatus;              /*!< Ethernet link status        */
745 
746         ETH_DMADescTypeDef * RxDesc;      /*!< Rx descriptor to Get        */
747 
748         ETH_DMADescTypeDef * TxDesc;      /*!< Tx descriptor to Set        */
749 
750         ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos         */
751 
752         __IO HAL_ETH_StateTypeDef State;  /*!< ETH communication state     */
753 
754         HAL_LockTypeDef Lock;             /*!< ETH Lock                    */
755     } ETH_HandleTypeDef;
756 
757 /**
758  * @}
759  */
760 
761 /* Exported constants --------------------------------------------------------*/
762 
763 /** @defgroup ETH_Exported_Constants ETH Exported Constants
764  * @{
765  */
766 
767 /** @defgroup ETH_Buffers_setting ETH Buffers setting
768  * @{
769  */
770     #define ETH_MAX_PACKET_SIZE        ( ( uint32_t ) 1536U ) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
771     #define ETH_HEADER                 ( ( uint32_t ) 14U )   /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
772     #define ETH_CRC                    ( ( uint32_t ) 4U )    /*!< Ethernet CRC */
773     #define ETH_EXTRA                  ( ( uint32_t ) 2U )    /*!< Extra bytes in some cases */
774     #define ETH_VLAN_TAG               ( ( uint32_t ) 4U )    /*!< optional 802.1q VLAN Tag */
775     #define ETH_MIN_ETH_PAYLOAD        ( ( uint32_t ) 46U )   /*!< Minimum Ethernet payload size */
776     #define ETH_MAX_ETH_PAYLOAD        ( ( uint32_t ) 1500U ) /*!< Maximum Ethernet payload size */
777     #define ETH_JUMBO_FRAME_PAYLOAD    ( ( uint32_t ) 9000U ) /*!< Jumbo frame payload size */
778 
779 /* Ethernet driver receive buffers are organized in a chained linked-list, when
780  * an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
781  * to the driver receive buffers memory.
782  *
783  * Depending on the size of the received Ethernet packet and the size of
784  * each Ethernet driver receive buffer, the received packet can take one or more
785  * Ethernet driver receive buffer.
786  *
787  * In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE
788  * and the total count of the driver receive buffers ETH_RXBUFNB.
789  *
790  * The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
791  * example, they can be reconfigured in the application layer to fit the application
792  * needs */
793 
794 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
795  * packet */
796     #ifndef ETH_RX_BUF_SIZE
797         #error please define ETH_RX_BUF_SIZE
798         #define ETH_RX_BUF_SIZE    ETH_MAX_PACKET_SIZE
799     #endif
800 
801 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
802     #ifndef ETH_RXBUFNB
803         #define ETH_RXBUFNB    ( ( uint32_t ) 5U )  /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
804     #endif
805 
806 
807 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
808  * an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the
809  * driver transmit buffers memory to the TxFIFO.
810  *
811  * Depending on the size of the Ethernet packet to be transmitted and the size of
812  * each Ethernet driver transmit buffer, the packet to be transmitted can take
813  * one or more Ethernet driver transmit buffer.
814  *
815  * In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE
816  * and the total count of the driver transmit buffers ETH_TXBUFNB.
817  *
818  * The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
819  * example, they can be reconfigured in the application layer to fit the application
820  * needs */
821 
822 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
823  * packet */
824     #ifndef ETH_TX_BUF_SIZE
825         #error please define ETH_TX_BUF_SIZE
826         #define ETH_TX_BUF_SIZE    ETH_MAX_PACKET_SIZE
827     #endif
828 
829 /* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/
830     #ifndef ETH_TXBUFNB
831         #define ETH_TXBUFNB    ( ( uint32_t ) 5U )   /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
832     #endif
833 
834 /**
835  * @}
836  */
837 
838 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
839  * @{
840  */
841 
842 /*
843  * DMA Tx Descriptor
844  * -----------------------------------------------------------------------------------------------
845  * TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
846  * -----------------------------------------------------------------------------------------------
847  * TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
848  * -----------------------------------------------------------------------------------------------
849  * TDES2 |                         Buffer1 Address [31:0]                                         |
850  * -----------------------------------------------------------------------------------------------
851  * TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
852  * -----------------------------------------------------------------------------------------------
853  */
854 
855 /**
856  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
857  */
858     #define ETH_DMATXDESC_OWN                       ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine */
859     #define ETH_DMATXDESC_IC                        ( ( uint32_t ) 0x40000000U ) /*!< Interrupt on Completion */
860     #define ETH_DMATXDESC_LS                        ( ( uint32_t ) 0x20000000U ) /*!< Last Segment */
861     #define ETH_DMATXDESC_FS                        ( ( uint32_t ) 0x10000000U ) /*!< First Segment */
862     #define ETH_DMATXDESC_DC                        ( ( uint32_t ) 0x08000000U ) /*!< Disable CRC */
863     #define ETH_DMATXDESC_DP                        ( ( uint32_t ) 0x04000000U ) /*!< Disable Padding */
864     #define ETH_DMATXDESC_TTSE                      ( ( uint32_t ) 0x02000000U ) /*!< Transmit Time Stamp Enable */
865     #define ETH_DMATXDESC_CIC                       ( ( uint32_t ) 0x00C00000U ) /*!< Checksum Insertion Control: 4 cases */
866     #define ETH_DMATXDESC_CIC_BYPASS                ( ( uint32_t ) 0x00000000U ) /*!< Do Nothing: Checksum Engine is bypassed */
867     #define ETH_DMATXDESC_CIC_IPV4HEADER            ( ( uint32_t ) 0x00400000U ) /*!< IPV4 header Checksum Insertion */
868     #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT    ( ( uint32_t ) 0x00800000U ) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
869     #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL       ( ( uint32_t ) 0x00C00000U ) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
870     #define ETH_DMATXDESC_TER                       ( ( uint32_t ) 0x00200000U ) /*!< Transmit End of Ring */
871     #define ETH_DMATXDESC_TCH                       ( ( uint32_t ) 0x00100000U ) /*!< Second Address Chained */
872     #define ETH_DMATXDESC_TTSS                      ( ( uint32_t ) 0x00020000U ) /*!< Tx Time Stamp Status */
873     #define ETH_DMATXDESC_IHE                       ( ( uint32_t ) 0x00010000U ) /*!< IP Header Error */
874     #define ETH_DMATXDESC_ES                        ( ( uint32_t ) 0x00008000U ) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
875     #define ETH_DMATXDESC_JT                        ( ( uint32_t ) 0x00004000U ) /*!< Jabber Timeout */
876     #define ETH_DMATXDESC_FF                        ( ( uint32_t ) 0x00002000U ) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
877     #define ETH_DMATXDESC_PCE                       ( ( uint32_t ) 0x00001000U ) /*!< Payload Checksum Error */
878     #define ETH_DMATXDESC_LCA                       ( ( uint32_t ) 0x00000800U ) /*!< Loss of Carrier: carrier lost during transmission */
879     #define ETH_DMATXDESC_NC                        ( ( uint32_t ) 0x00000400U ) /*!< No Carrier: no carrier signal from the transceiver */
880     #define ETH_DMATXDESC_LCO                       ( ( uint32_t ) 0x00000200U ) /*!< Late Collision: transmission aborted due to collision */
881     #define ETH_DMATXDESC_EC                        ( ( uint32_t ) 0x00000100U ) /*!< Excessive Collision: transmission aborted after 16 collisions */
882     #define ETH_DMATXDESC_VF                        ( ( uint32_t ) 0x00000080U ) /*!< VLAN Frame */
883     #define ETH_DMATXDESC_CC                        ( ( uint32_t ) 0x00000078U ) /*!< Collision Count */
884     #define ETH_DMATXDESC_ED                        ( ( uint32_t ) 0x00000004U ) /*!< Excessive Deferral */
885     #define ETH_DMATXDESC_UF                        ( ( uint32_t ) 0x00000002U ) /*!< Underflow Error: late data arrival from the memory */
886     #define ETH_DMATXDESC_DB                        ( ( uint32_t ) 0x00000001U ) /*!< Deferred Bit */
887 
888 /**
889  * @brief  Bit definition of TDES1 register
890  */
891     #define ETH_DMATXDESC_TBS2                      ( ( uint32_t ) 0x1FFF0000U ) /*!< Transmit Buffer2 Size */
892     #define ETH_DMATXDESC_TBS1                      ( ( uint32_t ) 0x00001FFFU ) /*!< Transmit Buffer1 Size */
893 
894 /**
895  * @brief  Bit definition of TDES2 register
896  */
897     #define ETH_DMATXDESC_B1AP                      ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer1 Address Pointer */
898 
899 /**
900  * @brief  Bit definition of TDES3 register
901  */
902     #define ETH_DMATXDESC_B2AP                      ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer2 Address Pointer */
903 
904 /*---------------------------------------------------------------------------------------------
905  * TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
906  * -----------------------------------------------------------------------------------------------
907  * TDES7 |                         Transmit Time Stamp High [31:0]                                |
908  * ----------------------------------------------------------------------------------------------*/
909 
910 /* Bit definition of TDES6 register */
911     #define ETH_DMAPTPTXDESC_TTSL    ( ( uint32_t ) 0xFFFFFFFFU ) /* Transmit Time Stamp Low */
912 
913 /* Bit definition of TDES7 register */
914     #define ETH_DMAPTPTXDESC_TTSH    ( ( uint32_t ) 0xFFFFFFFFU ) /* Transmit Time Stamp High */
915 
916 /**
917  * @}
918  */
919 
920 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
921  * @{
922  */
923 
924 /*
925  * DMA Rx Descriptor
926  * --------------------------------------------------------------------------------------------------------------------
927  * RDES0 | OWN(31) |                                             Status [30:0]                                          |
928  * ---------------------------------------------------------------------------------------------------------------------
929  * RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
930  * ---------------------------------------------------------------------------------------------------------------------
931  * RDES2 |                                       Buffer1 Address [31:0]                                                 |
932  * ---------------------------------------------------------------------------------------------------------------------
933  * RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
934  * ---------------------------------------------------------------------------------------------------------------------
935  */
936 
937 /**
938  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
939  */
940     #define ETH_DMARXDESC_OWN        ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine  */
941     #define ETH_DMARXDESC_AFM        ( ( uint32_t ) 0x40000000U ) /*!< DA Filter Fail for the rx frame  */
942     #define ETH_DMARXDESC_FL         ( ( uint32_t ) 0x3FFF0000U ) /*!< Receive descriptor frame length  */
943     #define ETH_DMARXDESC_ES         ( ( uint32_t ) 0x00008000U ) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
944     #define ETH_DMARXDESC_DE         ( ( uint32_t ) 0x00004000U ) /*!< Descriptor error: no more descriptors for receive frame  */
945     #define ETH_DMARXDESC_SAF        ( ( uint32_t ) 0x00002000U ) /*!< SA Filter Fail for the received frame */
946     #define ETH_DMARXDESC_LE         ( ( uint32_t ) 0x00001000U ) /*!< Frame size not matching with length field */
947     #define ETH_DMARXDESC_OE         ( ( uint32_t ) 0x00000800U ) /*!< Overflow Error: Frame was damaged due to buffer overflow */
948     #define ETH_DMARXDESC_VLAN       ( ( uint32_t ) 0x00000400U ) /*!< VLAN Tag: received frame is a VLAN frame */
949     #define ETH_DMARXDESC_FS         ( ( uint32_t ) 0x00000200U ) /*!< First descriptor of the frame  */
950     #define ETH_DMARXDESC_LS         ( ( uint32_t ) 0x00000100U ) /*!< Last descriptor of the frame  */
951     #define ETH_DMARXDESC_IPV4HCE    ( ( uint32_t ) 0x00000080U ) /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */
952     #define ETH_DMARXDESC_LC         ( ( uint32_t ) 0x00000040U ) /*!< Late collision occurred during reception   */
953     #define ETH_DMARXDESC_FT         ( ( uint32_t ) 0x00000020U ) /*!< Frame type - Ethernet, otherwise 802.3    */
954     #define ETH_DMARXDESC_RWT        ( ( uint32_t ) 0x00000010U ) /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
955     #define ETH_DMARXDESC_RE         ( ( uint32_t ) 0x00000008U ) /*!< Receive error: error reported by MII interface  */
956     #define ETH_DMARXDESC_DBE        ( ( uint32_t ) 0x00000004U ) /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
957     #define ETH_DMARXDESC_CE         ( ( uint32_t ) 0x00000002U ) /*!< CRC error */
958     #define ETH_DMARXDESC_MAMPCE     ( ( uint32_t ) 0x00000001U ) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
959 
960 /**
961  * @brief  Bit definition of RDES1 register
962  */
963     #define ETH_DMARXDESC_DIC        ( ( uint32_t ) 0x80000000U ) /*!< Disable Interrupt on Completion */
964     #define ETH_DMARXDESC_RBS2       ( ( uint32_t ) 0x1FFF0000U ) /*!< Receive Buffer2 Size */
965     #define ETH_DMARXDESC_RER        ( ( uint32_t ) 0x00008000U ) /*!< Receive End of Ring */
966     #define ETH_DMARXDESC_RCH        ( ( uint32_t ) 0x00004000U ) /*!< Second Address Chained */
967     #define ETH_DMARXDESC_RBS1       ( ( uint32_t ) 0x00001FFFU ) /*!< Receive Buffer1 Size */
968 
969 /**
970  * @brief  Bit definition of RDES2 register
971  */
972     #define ETH_DMARXDESC_B1AP       ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer1 Address Pointer */
973 
974 /**
975  * @brief  Bit definition of RDES3 register
976  */
977     #define ETH_DMARXDESC_B2AP       ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer2 Address Pointer */
978 
979 /*---------------------------------------------------------------------------------------------------------------------
980  * RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
981  * ---------------------------------------------------------------------------------------------------------------------
982  * RDES5 |                                            Reserved[31:0]                                                    |
983  * ---------------------------------------------------------------------------------------------------------------------
984  * RDES6 |                                       Receive Time Stamp Low [31:0]                                          |
985  * ---------------------------------------------------------------------------------------------------------------------
986  * RDES7 |                                       Receive Time Stamp High [31:0]                                         |
987  * --------------------------------------------------------------------------------------------------------------------*/
988 
989 /* Bit definition of RDES4 register */
990     #define ETH_DMAPTPRXDESC_PTPV                               ( ( uint32_t ) 0x00002000U ) /* PTP Version */
991     #define ETH_DMAPTPRXDESC_PTPFT                              ( ( uint32_t ) 0x00001000U ) /* PTP Frame Type */
992     #define ETH_DMAPTPRXDESC_PTPMT                              ( ( uint32_t ) 0x00000F00U ) /* PTP Message Type */
993     #define ETH_DMAPTPRXDESC_PTPMT_SYNC                         ( ( uint32_t ) 0x00000100U ) /* SYNC message (all clock types) */
994     #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                     ( ( uint32_t ) 0x00000200U ) /* FollowUp message (all clock types) */
995     #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                     ( ( uint32_t ) 0x00000300U ) /* DelayReq message (all clock types) */
996     #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                    ( ( uint32_t ) 0x00000400U ) /* DelayResp message (all clock types) */
997     #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE           ( ( uint32_t ) 0x00000500U ) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
998     #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG             ( ( uint32_t ) 0x00000600U ) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */
999     #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL    ( ( uint32_t ) 0x00000700U ) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
1000     #define ETH_DMAPTPRXDESC_IPV6PR                             ( ( uint32_t ) 0x00000080U ) /* IPv6 Packet Received */
1001     #define ETH_DMAPTPRXDESC_IPV4PR                             ( ( uint32_t ) 0x00000040U ) /* IPv4 Packet Received */
1002     #define ETH_DMAPTPRXDESC_IPCB                               ( ( uint32_t ) 0x00000020U ) /* IP Checksum Bypassed */
1003     #define ETH_DMAPTPRXDESC_IPPE                               ( ( uint32_t ) 0x00000010U ) /* IP Payload Error */
1004     #define ETH_DMAPTPRXDESC_IPHE                               ( ( uint32_t ) 0x00000008U ) /* IP Header Error */
1005     #define ETH_DMAPTPRXDESC_IPPT                               ( ( uint32_t ) 0x00000007U ) /* IP Payload Type */
1006     #define ETH_DMAPTPRXDESC_IPPT_UDP                           ( ( uint32_t ) 0x00000001U ) /* UDP payload encapsulated in the IP datagram */
1007     #define ETH_DMAPTPRXDESC_IPPT_TCP                           ( ( uint32_t ) 0x00000002U ) /* TCP payload encapsulated in the IP datagram */
1008     #define ETH_DMAPTPRXDESC_IPPT_ICMP                          ( ( uint32_t ) 0x00000003U ) /* ICMP payload encapsulated in the IP datagram */
1009 
1010 /* Bit definition of RDES6 register */
1011     #define ETH_DMAPTPRXDESC_RTSL                               ( ( uint32_t ) 0xFFFFFFFFU ) /* Receive Time Stamp Low */
1012 
1013 /* Bit definition of RDES7 register */
1014     #define ETH_DMAPTPRXDESC_RTSH                               ( ( uint32_t ) 0xFFFFFFFFU ) /* Receive Time Stamp High */
1015 
1016 /**
1017  * @}
1018  */
1019 
1020 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
1021  * @{
1022  */
1023     #define ETH_AUTONEGOTIATION_ENABLE     ( ( uint32_t ) 0x00000001U )
1024     #define ETH_AUTONEGOTIATION_DISABLE    ( ( uint32_t ) 0x00000000U )
1025 
1026 /**
1027  * @}
1028  */
1029 
1030 /** @defgroup ETH_Speed ETH Speed
1031  * @{
1032  */
1033     #define ETH_SPEED_10M     ( ( uint32_t ) 0x00000000U )
1034     #define ETH_SPEED_100M    ( ( uint32_t ) 0x00004000U )
1035 
1036 /**
1037  * @}
1038  */
1039 
1040 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
1041  * @{
1042  */
1043     #define ETH_MODE_FULLDUPLEX    ( ( uint32_t ) 0x00000800U )
1044     #define ETH_MODE_HALFDUPLEX    ( ( uint32_t ) 0x00000000U )
1045 
1046 /**
1047  * @}
1048  */
1049 
1050 /** @defgroup ETH_Rx_Mode ETH Rx Mode
1051  * @{
1052  */
1053     #define ETH_RXPOLLING_MODE      ( ( uint32_t ) 0x00000000U )
1054     #define ETH_RXINTERRUPT_MODE    ( ( uint32_t ) 0x00000001U )
1055 
1056 /**
1057  * @}
1058  */
1059 
1060 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
1061  * @{
1062  */
1063     #define ETH_CHECKSUM_BY_HARDWARE    ( ( uint32_t ) 0x00000000U )
1064     #define ETH_CHECKSUM_BY_SOFTWARE    ( ( uint32_t ) 0x00000001U )
1065 
1066 /**
1067  * @}
1068  */
1069 
1070 /** @defgroup ETH_Media_Interface ETH Media Interface
1071  * @{
1072  */
1073     #define ETH_MEDIA_INTERFACE_MII     ( ( uint32_t ) 0x00000000U )
1074     #define ETH_MEDIA_INTERFACE_RMII    ( ( uint32_t ) SYSCFG_PMC_MII_RMII_SEL )
1075 
1076 /**
1077  * @}
1078  */
1079 
1080 /** @defgroup ETH_Watchdog ETH Watchdog
1081  * @{
1082  */
1083     #define ETH_WATCHDOG_ENABLE     ( ( uint32_t ) 0x00000000U )
1084     #define ETH_WATCHDOG_DISABLE    ( ( uint32_t ) 0x00800000U )
1085 
1086 /**
1087  * @}
1088  */
1089 
1090 /** @defgroup ETH_Jabber ETH Jabber
1091  * @{
1092  */
1093     #define ETH_JABBER_ENABLE     ( ( uint32_t ) 0x00000000U )
1094     #define ETH_JABBER_DISABLE    ( ( uint32_t ) 0x00400000U )
1095 
1096 /**
1097  * @}
1098  */
1099 
1100 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
1101  * @{
1102  */
1103     #define ETH_INTERFRAMEGAP_96BIT    ( ( uint32_t ) 0x00000000U ) /*!< minimum IFG between frames during transmission is 96Bit */
1104     #define ETH_INTERFRAMEGAP_88BIT    ( ( uint32_t ) 0x00020000U ) /*!< minimum IFG between frames during transmission is 88Bit */
1105     #define ETH_INTERFRAMEGAP_80BIT    ( ( uint32_t ) 0x00040000U ) /*!< minimum IFG between frames during transmission is 80Bit */
1106     #define ETH_INTERFRAMEGAP_72BIT    ( ( uint32_t ) 0x00060000U ) /*!< minimum IFG between frames during transmission is 72Bit */
1107     #define ETH_INTERFRAMEGAP_64BIT    ( ( uint32_t ) 0x00080000U ) /*!< minimum IFG between frames during transmission is 64Bit */
1108     #define ETH_INTERFRAMEGAP_56BIT    ( ( uint32_t ) 0x000A0000U ) /*!< minimum IFG between frames during transmission is 56Bit */
1109     #define ETH_INTERFRAMEGAP_48BIT    ( ( uint32_t ) 0x000C0000U ) /*!< minimum IFG between frames during transmission is 48Bit */
1110     #define ETH_INTERFRAMEGAP_40BIT    ( ( uint32_t ) 0x000E0000U ) /*!< minimum IFG between frames during transmission is 40Bit */
1111 
1112 /**
1113  * @}
1114  */
1115 
1116 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
1117  * @{
1118  */
1119     #define ETH_CARRIERSENCE_ENABLE     ( ( uint32_t ) 0x00000000U )
1120     #define ETH_CARRIERSENCE_DISABLE    ( ( uint32_t ) 0x00010000U )
1121 
1122 /**
1123  * @}
1124  */
1125 
1126 /** @defgroup ETH_Receive_Own ETH Receive Own
1127  * @{
1128  */
1129     #define ETH_RECEIVEOWN_ENABLE     ( ( uint32_t ) 0x00000000U )
1130     #define ETH_RECEIVEOWN_DISABLE    ( ( uint32_t ) 0x00002000U )
1131 
1132 /**
1133  * @}
1134  */
1135 
1136 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
1137  * @{
1138  */
1139     #define ETH_LOOPBACKMODE_ENABLE     ( ( uint32_t ) 0x00001000U )
1140     #define ETH_LOOPBACKMODE_DISABLE    ( ( uint32_t ) 0x00000000U )
1141 
1142 /**
1143  * @}
1144  */
1145 
1146 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
1147  * @{
1148  */
1149     #define ETH_CHECKSUMOFFLAOD_ENABLE     ( ( uint32_t ) 0x00000400U )
1150     #define ETH_CHECKSUMOFFLAOD_DISABLE    ( ( uint32_t ) 0x00000000U )
1151 
1152 /**
1153  * @}
1154  */
1155 
1156 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
1157  * @{
1158  */
1159     #define ETH_RETRYTRANSMISSION_ENABLE     ( ( uint32_t ) 0x00000000U )
1160     #define ETH_RETRYTRANSMISSION_DISABLE    ( ( uint32_t ) 0x00000200U )
1161 
1162 /**
1163  * @}
1164  */
1165 
1166 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
1167  * @{
1168  */
1169     #define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ( ( uint32_t ) 0x00000080U )
1170     #define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ( ( uint32_t ) 0x00000000U )
1171 
1172 /**
1173  * @}
1174  */
1175 
1176 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1177  * @{
1178  */
1179     #define ETH_BACKOFFLIMIT_10    ( ( uint32_t ) 0x00000000U )
1180     #define ETH_BACKOFFLIMIT_8     ( ( uint32_t ) 0x00000020U )
1181     #define ETH_BACKOFFLIMIT_4     ( ( uint32_t ) 0x00000040U )
1182     #define ETH_BACKOFFLIMIT_1     ( ( uint32_t ) 0x00000060U )
1183 
1184 /**
1185  * @}
1186  */
1187 
1188 /** @defgroup ETH_Deferral_Check ETH Deferral Check
1189  * @{
1190  */
1191     #define ETH_DEFFERRALCHECK_ENABLE     ( ( uint32_t ) 0x00000010U )
1192     #define ETH_DEFFERRALCHECK_DISABLE    ( ( uint32_t ) 0x00000000U )
1193 
1194 /**
1195  * @}
1196  */
1197 
1198 /** @defgroup ETH_Receive_All ETH Receive All
1199  * @{
1200  */
1201     #define ETH_RECEIVEALL_ENABLE     ( ( uint32_t ) 0x80000000U )
1202     #define ETH_RECEIVEAll_DISABLE    ( ( uint32_t ) 0x00000000U )
1203 
1204 /**
1205  * @}
1206  */
1207 
1208 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
1209  * @{
1210  */
1211     #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE     ( ( uint32_t ) 0x00000200U )
1212     #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE    ( ( uint32_t ) 0x00000300U )
1213     #define ETH_SOURCEADDRFILTER_DISABLE           ( ( uint32_t ) 0x00000000U )
1214 
1215 /**
1216  * @}
1217  */
1218 
1219 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
1220  * @{
1221  */
1222     #define ETH_PASSCONTROLFRAMES_BLOCKALL                   ( ( uint32_t ) 0x00000040U ) /*!< MAC filters all control frames from reaching the application */
1223     #define ETH_PASSCONTROLFRAMES_FORWARDALL                 ( ( uint32_t ) 0x00000080U ) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
1224     #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER    ( ( uint32_t ) 0x000000C0U ) /*!< MAC forwards control frames that pass the Address Filter. */
1225 
1226 /**
1227  * @}
1228  */
1229 
1230 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
1231  * @{
1232  */
1233     #define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ( ( uint32_t ) 0x00000000U )
1234     #define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ( ( uint32_t ) 0x00000020U )
1235 
1236 /**
1237  * @}
1238  */
1239 
1240 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
1241  * @{
1242  */
1243     #define ETH_DESTINATIONADDRFILTER_NORMAL     ( ( uint32_t ) 0x00000000U )
1244     #define ETH_DESTINATIONADDRFILTER_INVERSE    ( ( uint32_t ) 0x00000008U )
1245 
1246 /**
1247  * @}
1248  */
1249 
1250 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
1251  * @{
1252  */
1253     #define ETH_PROMISCUOUS_MODE_ENABLE     ( ( uint32_t ) 0x00000001U )
1254     #define ETH_PROMISCUOUS_MODE_DISABLE    ( ( uint32_t ) 0x00000000U )
1255 
1256 /**
1257  * @}
1258  */
1259 
1260 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
1261  * @{
1262  */
1263     #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ( ( uint32_t ) 0x00000404U )
1264     #define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ( ( uint32_t ) 0x00000004U )
1265     #define ETH_MULTICASTFRAMESFILTER_PERFECT             ( ( uint32_t ) 0x00000000U )
1266     #define ETH_MULTICASTFRAMESFILTER_NONE                ( ( uint32_t ) 0x00000010U )
1267 
1268 /**
1269  * @}
1270  */
1271 
1272 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
1273  * @{
1274  */
1275     #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE    ( ( uint32_t ) 0x00000402U )
1276     #define ETH_UNICASTFRAMESFILTER_HASHTABLE           ( ( uint32_t ) 0x00000002U )
1277     #define ETH_UNICASTFRAMESFILTER_PERFECT             ( ( uint32_t ) 0x00000000U )
1278 
1279 /**
1280  * @}
1281  */
1282 
1283 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
1284  * @{
1285  */
1286     #define ETH_ZEROQUANTAPAUSE_ENABLE     ( ( uint32_t ) 0x00000000U )
1287     #define ETH_ZEROQUANTAPAUSE_DISABLE    ( ( uint32_t ) 0x00000080U )
1288 
1289 /**
1290  * @}
1291  */
1292 
1293 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1294  * @{
1295  */
1296     #define ETH_PAUSELOWTHRESHOLD_MINUS4      ( ( uint32_t ) 0x00000000U ) /*!< Pause time minus 4 slot times */
1297     #define ETH_PAUSELOWTHRESHOLD_MINUS28     ( ( uint32_t ) 0x00000010U ) /*!< Pause time minus 28 slot times */
1298     #define ETH_PAUSELOWTHRESHOLD_MINUS144    ( ( uint32_t ) 0x00000020U ) /*!< Pause time minus 144 slot times */
1299     #define ETH_PAUSELOWTHRESHOLD_MINUS256    ( ( uint32_t ) 0x00000030U ) /*!< Pause time minus 256 slot times */
1300 
1301 /**
1302  * @}
1303  */
1304 
1305 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
1306  * @{
1307  */
1308     #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE     ( ( uint32_t ) 0x00000008U )
1309     #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE    ( ( uint32_t ) 0x00000000U )
1310 
1311 /**
1312  * @}
1313  */
1314 
1315 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
1316  * @{
1317  */
1318     #define ETH_RECEIVEFLOWCONTROL_ENABLE     ( ( uint32_t ) 0x00000004U )
1319     #define ETH_RECEIVEFLOWCONTROL_DISABLE    ( ( uint32_t ) 0x00000000U )
1320 
1321 /**
1322  * @}
1323  */
1324 
1325 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
1326  * @{
1327  */
1328     #define ETH_TRANSMITFLOWCONTROL_ENABLE     ( ( uint32_t ) 0x00000002U )
1329     #define ETH_TRANSMITFLOWCONTROL_DISABLE    ( ( uint32_t ) 0x00000000U )
1330 
1331 /**
1332  * @}
1333  */
1334 
1335 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1336  * @{
1337  */
1338     #define ETH_VLANTAGCOMPARISON_12BIT    ( ( uint32_t ) 0x00010000U )
1339     #define ETH_VLANTAGCOMPARISON_16BIT    ( ( uint32_t ) 0x00000000U )
1340 
1341 /**
1342  * @}
1343  */
1344 
1345 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1346  * @{
1347  */
1348     #define ETH_MAC_ADDRESS0    ( ( uint32_t ) 0x00000000U )
1349     #define ETH_MAC_ADDRESS1    ( ( uint32_t ) 0x00000008U )
1350     #define ETH_MAC_ADDRESS2    ( ( uint32_t ) 0x00000010U )
1351     #define ETH_MAC_ADDRESS3    ( ( uint32_t ) 0x00000018U )
1352 
1353 /**
1354  * @}
1355  */
1356 
1357 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
1358  * @{
1359  */
1360     #define ETH_MAC_ADDRESSFILTER_SA    ( ( uint32_t ) 0x00000000U )
1361     #define ETH_MAC_ADDRESSFILTER_DA    ( ( uint32_t ) 0x00000008U )
1362 
1363 /**
1364  * @}
1365  */
1366 
1367 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
1368  * @{
1369  */
1370     #define ETH_MAC_ADDRESSMASK_BYTE6    ( ( uint32_t ) 0x20000000U ) /*!< Mask MAC Address high reg bits [15:8] */
1371     #define ETH_MAC_ADDRESSMASK_BYTE5    ( ( uint32_t ) 0x10000000U ) /*!< Mask MAC Address high reg bits [7:0] */
1372     #define ETH_MAC_ADDRESSMASK_BYTE4    ( ( uint32_t ) 0x08000000U ) /*!< Mask MAC Address low reg bits [31:24] */
1373     #define ETH_MAC_ADDRESSMASK_BYTE3    ( ( uint32_t ) 0x04000000U ) /*!< Mask MAC Address low reg bits [23:16] */
1374     #define ETH_MAC_ADDRESSMASK_BYTE2    ( ( uint32_t ) 0x02000000U ) /*!< Mask MAC Address low reg bits [15:8] */
1375     #define ETH_MAC_ADDRESSMASK_BYTE1    ( ( uint32_t ) 0x01000000U ) /*!< Mask MAC Address low reg bits [70] */
1376 
1377 /**
1378  * @}
1379  */
1380 
1381 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
1382  * @{
1383  */
1384     #ifndef ETH_MAC_TXFIFO_FULL
1385         #define ETH_MAC_TXFIFO_FULL                              ( ( uint32_t ) 0x02000000 )         /* Tx FIFO full */
1386         #define ETH_MAC_TXFIFONOT_EMPTY                          ( ( uint32_t ) 0x01000000 )         /* Tx FIFO not empty */
1387         #define ETH_MAC_TXFIFO_WRITE_ACTIVE                      ( ( uint32_t ) 0x00400000 )         /* Tx FIFO write active */
1388         #define ETH_MAC_TXFIFO_IDLE                              ( ( uint32_t ) 0x00000000 )         /* Tx FIFO read status: Idle */
1389         #define ETH_MAC_TXFIFO_READ                              ( ( uint32_t ) 0x00100000 )         /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
1390         #define ETH_MAC_TXFIFO_WAITING                           ( ( uint32_t ) 0x00200000 )         /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
1391         #define ETH_MAC_TXFIFO_WRITING                           ( ( uint32_t ) 0x00300000 )         /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
1392         #define ETH_MAC_TRANSMISSION_PAUSE                       ( ( uint32_t ) 0x00080000 )         /* MAC transmitter in pause */
1393         #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE             ( ( uint32_t ) 0x00000000 )         /* MAC transmit frame controller: Idle */
1394         #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING          ( ( uint32_t ) 0x00020000 )         /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
1395         #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF    ( ( uint32_t ) 0x00040000 )         /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
1396         #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING     ( ( uint32_t ) 0x00060000 )         /* MAC transmit frame controller: Transferring input frame for transmission */
1397         #define ETH_MAC_MII_TRANSMIT_ACTIVE                      ( ( uint32_t ) 0x00010000 )         /* MAC MII transmit engine active */
1398         #define ETH_MAC_RXFIFO_EMPTY                             ( ( uint32_t ) 0x00000000 )         /* Rx FIFO fill level: empty */
1399         #define ETH_MAC_RXFIFO_BELOW_THRESHOLD                   ( ( uint32_t ) 0x00000100 )         /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
1400         #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD                   ( ( uint32_t ) 0x00000200 )         /* Rx FIFO fill level: fill-level above flow-control activate threshold */
1401         #define ETH_MAC_RXFIFO_FULL                              ( ( uint32_t ) 0x00000300 )         /* Rx FIFO fill level: full */
1402         #define ETH_MAC_READCONTROLLER_IDLE                      ( ( uint32_t ) 0x00000060 )         /* Rx FIFO read controller IDLE state */
1403         #define ETH_MAC_READCONTROLLER_READING_DATA              ( ( uint32_t ) 0x00000060 )         /* Rx FIFO read controller Reading frame data */
1404         #define ETH_MAC_READCONTROLLER_READING_STATUS            ( ( uint32_t ) 0x00000060 )         /* Rx FIFO read controller Reading frame status (or time-stamp) */
1405         #define ETH_MAC_READCONTROLLER_                          FLUSHING( ( uint32_t ) 0x00000060 ) /* Rx FIFO read controller Flushing the frame data and status */
1406         #define ETH_MAC_RXFIFO_WRITE_ACTIVE                      ( ( uint32_t ) 0x00000010 )         /* Rx FIFO write controller active */
1407         #define ETH_MAC_SMALL_FIFO_NOTACTIVE                     ( ( uint32_t ) 0x00000000 )         /* MAC small FIFO read / write controllers not active */
1408         #define ETH_MAC_SMALL_FIFO_READ_ACTIVE                   ( ( uint32_t ) 0x00000002 )         /* MAC small FIFO read controller active */
1409         #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE                  ( ( uint32_t ) 0x00000004 )         /* MAC small FIFO write controller active */
1410         #define ETH_MAC_SMALL_FIFO_RW_ACTIVE                     ( ( uint32_t ) 0x00000006 )         /* MAC small FIFO read / write controllers active */
1411         #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE              ( ( uint32_t ) 0x00000001 )         /* MAC MII receive protocol engine active */
1412     #else /* ifndef ETH_MAC_TXFIFO_FULL */
1413         /* stm32_hal_legacy.h has probably been included. That file defines 'ETH_MAC_TXFIFO_FULL' and all macro's here below. */
1414     #endif /* ifndef ETH_MAC_TXFIFO_FULL */
1415 
1416 /**
1417  * @}
1418  */
1419 
1420 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
1421  * @{
1422  */
1423     #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE     ( ( uint32_t ) 0x00000000U )
1424     #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE    ( ( uint32_t ) 0x04000000U )
1425 
1426 /**
1427  * @}
1428  */
1429 
1430 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
1431  * @{
1432  */
1433     #define ETH_RECEIVESTOREFORWARD_ENABLE     ( ( uint32_t ) 0x02000000U )
1434     #define ETH_RECEIVESTOREFORWARD_DISABLE    ( ( uint32_t ) 0x00000000U )
1435 
1436 /**
1437  * @}
1438  */
1439 
1440 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
1441  * @{
1442  */
1443     #define ETH_FLUSHRECEIVEDFRAME_ENABLE     ( ( uint32_t ) 0x00000000U )
1444     #define ETH_FLUSHRECEIVEDFRAME_DISABLE    ( ( uint32_t ) 0x01000000U )
1445 
1446 /**
1447  * @}
1448  */
1449 
1450 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
1451  * @{
1452  */
1453     #define ETH_TRANSMITSTOREFORWARD_ENABLE     ( ( uint32_t ) 0x00200000U )
1454     #define ETH_TRANSMITSTOREFORWARD_DISABLE    ( ( uint32_t ) 0x00000000U )
1455 
1456 /**
1457  * @}
1458  */
1459 
1460 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
1461  * @{
1462  */
1463     #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ( ( uint32_t ) 0x00000000U ) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1464     #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ( ( uint32_t ) 0x00004000U ) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1465     #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ( ( uint32_t ) 0x00008000U ) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1466     #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ( ( uint32_t ) 0x0000C000U ) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1467     #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ( ( uint32_t ) 0x00010000U ) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1468     #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ( ( uint32_t ) 0x00014000U ) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1469     #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ( ( uint32_t ) 0x00018000U ) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1470     #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ( ( uint32_t ) 0x0001C000U ) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1471 
1472 /**
1473  * @}
1474  */
1475 
1476 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
1477  * @{
1478  */
1479     #define ETH_FORWARDERRORFRAMES_ENABLE     ( ( uint32_t ) 0x00000080U )
1480     #define ETH_FORWARDERRORFRAMES_DISABLE    ( ( uint32_t ) 0x00000000U )
1481 
1482 /**
1483  * @}
1484  */
1485 
1486 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
1487  * @{
1488  */
1489     #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE     ( ( uint32_t ) 0x00000040U )
1490     #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE    ( ( uint32_t ) 0x00000000U )
1491 
1492 /**
1493  * @}
1494  */
1495 
1496 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
1497  * @{
1498  */
1499     #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES     ( ( uint32_t ) 0x00000000U ) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1500     #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES     ( ( uint32_t ) 0x00000008U ) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1501     #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES     ( ( uint32_t ) 0x00000010U ) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1502     #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES    ( ( uint32_t ) 0x00000018U ) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1503 
1504 /**
1505  * @}
1506  */
1507 
1508 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
1509  * @{
1510  */
1511     #define ETH_SECONDFRAMEOPERARTE_ENABLE     ( ( uint32_t ) 0x00000004U )
1512     #define ETH_SECONDFRAMEOPERARTE_DISABLE    ( ( uint32_t ) 0x00000000U )
1513 
1514 /**
1515  * @}
1516  */
1517 
1518 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
1519  * @{
1520  */
1521     #define ETH_ADDRESSALIGNEDBEATS_ENABLE     ( ( uint32_t ) 0x02000000U )
1522     #define ETH_ADDRESSALIGNEDBEATS_DISABLE    ( ( uint32_t ) 0x00000000U )
1523 
1524 /**
1525  * @}
1526  */
1527 
1528 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
1529  * @{
1530  */
1531     #define ETH_FIXEDBURST_ENABLE     ( ( uint32_t ) 0x00010000U )
1532     #define ETH_FIXEDBURST_DISABLE    ( ( uint32_t ) 0x00000000U )
1533 
1534 /**
1535  * @}
1536  */
1537 
1538 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1539  * @{
1540  */
1541     #define ETH_RXDMABURSTLENGTH_1BEAT            ( ( uint32_t ) 0x00020000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1542     #define ETH_RXDMABURSTLENGTH_2BEAT            ( ( uint32_t ) 0x00040000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1543     #define ETH_RXDMABURSTLENGTH_4BEAT            ( ( uint32_t ) 0x00080000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1544     #define ETH_RXDMABURSTLENGTH_8BEAT            ( ( uint32_t ) 0x00100000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1545     #define ETH_RXDMABURSTLENGTH_16BEAT           ( ( uint32_t ) 0x00200000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1546     #define ETH_RXDMABURSTLENGTH_32BEAT           ( ( uint32_t ) 0x00400000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1547     #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT      ( ( uint32_t ) 0x01020000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1548     #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT      ( ( uint32_t ) 0x01040000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1549     #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT     ( ( uint32_t ) 0x01080000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1550     #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT     ( ( uint32_t ) 0x01100000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1551     #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT     ( ( uint32_t ) 0x01200000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1552     #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT    ( ( uint32_t ) 0x01400000U ) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1553 
1554 /**
1555  * @}
1556  */
1557 
1558 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1559  * @{
1560  */
1561     #define ETH_TXDMABURSTLENGTH_1BEAT            ( ( uint32_t ) 0x00000100U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1562     #define ETH_TXDMABURSTLENGTH_2BEAT            ( ( uint32_t ) 0x00000200U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1563     #define ETH_TXDMABURSTLENGTH_4BEAT            ( ( uint32_t ) 0x00000400U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1564     #define ETH_TXDMABURSTLENGTH_8BEAT            ( ( uint32_t ) 0x00000800U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1565     #define ETH_TXDMABURSTLENGTH_16BEAT           ( ( uint32_t ) 0x00001000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1566     #define ETH_TXDMABURSTLENGTH_32BEAT           ( ( uint32_t ) 0x00002000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1567     #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT      ( ( uint32_t ) 0x01000100U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1568     #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT      ( ( uint32_t ) 0x01000200U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1569     #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT     ( ( uint32_t ) 0x01000400U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1570     #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT     ( ( uint32_t ) 0x01000800U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1571     #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT     ( ( uint32_t ) 0x01001000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1572     #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT    ( ( uint32_t ) 0x01002000U ) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1573 
1574 /**
1575  * @}
1576  */
1577 
1578 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
1579  * @{
1580  */
1581     #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE     ( ( uint32_t ) 0x00000080U )
1582     #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE    ( ( uint32_t ) 0x00000000U )
1583 
1584 /**
1585  * @}
1586  */
1587 
1588 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1589  * @{
1590  */
1591     #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1    ( ( uint32_t ) 0x00000000U )
1592     #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1    ( ( uint32_t ) 0x00004000U )
1593     #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1    ( ( uint32_t ) 0x00008000U )
1594     #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1    ( ( uint32_t ) 0x0000C000U )
1595     #define ETH_DMAARBITRATION_RXPRIORTX              ( ( uint32_t ) 0x00000002U )
1596 
1597 /**
1598  * @}
1599  */
1600 
1601 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
1602  * @{
1603  */
1604     #define ETH_DMATXDESC_LASTSEGMENTS    ( ( uint32_t ) 0x40000000U ) /*!< Last Segment */
1605     #define ETH_DMATXDESC_FIRSTSEGMENT    ( ( uint32_t ) 0x20000000U ) /*!< First Segment */
1606 
1607 /**
1608  * @}
1609  */
1610 
1611 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
1612  * @{
1613  */
1614     #define ETH_DMATXDESC_CHECKSUMBYPASS               ( ( uint32_t ) 0x00000000U ) /*!< Checksum engine bypass */
1615     #define ETH_DMATXDESC_CHECKSUMIPV4HEADER           ( ( uint32_t ) 0x00400000U ) /*!< IPv4 header checksum insertion  */
1616     #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT    ( ( uint32_t ) 0x00800000U ) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1617     #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL       ( ( uint32_t ) 0x00C00000U ) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1618 
1619 /**
1620  * @}
1621  */
1622 
1623 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
1624  * @{
1625  */
1626     #define ETH_DMARXDESC_BUFFER1    ( ( uint32_t ) 0x00000000U ) /*!< DMA Rx Desc Buffer1 */
1627     #define ETH_DMARXDESC_BUFFER2    ( ( uint32_t ) 0x00000001U ) /*!< DMA Rx Desc Buffer2 */
1628 
1629 /**
1630  * @}
1631  */
1632 
1633 /** @defgroup ETH_PMT_Flags ETH PMT Flags
1634  * @{
1635  */
1636     #define ETH_PMT_FLAG_WUFFRPR    ( ( uint32_t ) 0x80000000U ) /*!< Wake-Up Frame Filter Register Pointer Reset */
1637     #define ETH_PMT_FLAG_WUFR       ( ( uint32_t ) 0x00000040U ) /*!< Wake-Up Frame Received */
1638     #define ETH_PMT_FLAG_MPR        ( ( uint32_t ) 0x00000020U ) /*!< Magic Packet Received */
1639 
1640 /**
1641  * @}
1642  */
1643 
1644 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
1645  * @{
1646  */
1647     #define ETH_MMC_IT_TGF       ( ( uint32_t ) 0x00200000U ) /*!< When Tx good frame counter reaches half the maximum value */
1648     #define ETH_MMC_IT_TGFMSC    ( ( uint32_t ) 0x00008000U ) /*!< When Tx good multi col counter reaches half the maximum value */
1649     #define ETH_MMC_IT_TGFSC     ( ( uint32_t ) 0x00004000U ) /*!< When Tx good single col counter reaches half the maximum value */
1650 
1651 /**
1652  * @}
1653  */
1654 
1655 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
1656  * @{
1657  */
1658     #define ETH_MMC_IT_RGUF    ( ( uint32_t ) 0x10020000U ) /*!< When Rx good unicast frames counter reaches half the maximum value */
1659     #define ETH_MMC_IT_RFAE    ( ( uint32_t ) 0x10000040U ) /*!< When Rx alignment error counter reaches half the maximum value */
1660     #define ETH_MMC_IT_RFCE    ( ( uint32_t ) 0x10000020U ) /*!< When Rx crc error counter reaches half the maximum value */
1661 
1662 /**
1663  * @}
1664  */
1665 
1666 /** @defgroup ETH_MAC_Flags ETH MAC Flags
1667  * @{
1668  */
1669     #define ETH_MAC_FLAG_TST     ( ( uint32_t ) 0x00000200U ) /*!< Time stamp trigger flag (on MAC) */
1670     #define ETH_MAC_FLAG_MMCT    ( ( uint32_t ) 0x00000040U ) /*!< MMC transmit flag  */
1671     #define ETH_MAC_FLAG_MMCR    ( ( uint32_t ) 0x00000020U ) /*!< MMC receive flag */
1672     #define ETH_MAC_FLAG_MMC     ( ( uint32_t ) 0x00000010U ) /*!< MMC flag (on MAC) */
1673     #define ETH_MAC_FLAG_PMT     ( ( uint32_t ) 0x00000008U ) /*!< PMT flag (on MAC) */
1674 
1675 /**
1676  * @}
1677  */
1678 
1679 /** @defgroup ETH_DMA_Flags ETH DMA Flags
1680  * @{
1681  */
1682     #define ETH_DMA_FLAG_TST                  ( ( uint32_t ) 0x20000000U ) /*!< Time-stamp trigger interrupt (on DMA) */
1683     #define ETH_DMA_FLAG_PMT                  ( ( uint32_t ) 0x10000000U ) /*!< PMT interrupt (on DMA) */
1684     #define ETH_DMA_FLAG_MMC                  ( ( uint32_t ) 0x08000000U ) /*!< MMC interrupt (on DMA) */
1685     #define ETH_DMA_FLAG_DATATRANSFERERROR    ( ( uint32_t ) 0x00800000U ) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1686     #define ETH_DMA_FLAG_READWRITEERROR       ( ( uint32_t ) 0x01000000U ) /*!< Error bits 0-write transfer, 1-read transfer */
1687     #define ETH_DMA_FLAG_ACCESSERROR          ( ( uint32_t ) 0x02000000U ) /*!< Error bits 0-data buffer, 1-desc. access */
1688     #define ETH_DMA_FLAG_NIS                  ( ( uint32_t ) 0x00010000U ) /*!< Normal interrupt summary flag */
1689     #define ETH_DMA_FLAG_AIS                  ( ( uint32_t ) 0x00008000U ) /*!< Abnormal interrupt summary flag */
1690     #define ETH_DMA_FLAG_ER                   ( ( uint32_t ) 0x00004000U ) /*!< Early receive flag */
1691     #define ETH_DMA_FLAG_FBE                  ( ( uint32_t ) 0x00002000U ) /*!< Fatal bus error flag */
1692     #define ETH_DMA_FLAG_ET                   ( ( uint32_t ) 0x00000400U ) /*!< Early transmit flag */
1693     #define ETH_DMA_FLAG_RWT                  ( ( uint32_t ) 0x00000200U ) /*!< Receive watchdog timeout flag */
1694     #define ETH_DMA_FLAG_RPS                  ( ( uint32_t ) 0x00000100U ) /*!< Receive process stopped flag */
1695     #define ETH_DMA_FLAG_RBU                  ( ( uint32_t ) 0x00000080U ) /*!< Receive buffer unavailable flag */
1696     #define ETH_DMA_FLAG_R                    ( ( uint32_t ) 0x00000040U ) /*!< Receive flag */
1697     #define ETH_DMA_FLAG_TU                   ( ( uint32_t ) 0x00000020U ) /*!< Underflow flag */
1698     #define ETH_DMA_FLAG_RO                   ( ( uint32_t ) 0x00000010U ) /*!< Overflow flag */
1699     #define ETH_DMA_FLAG_TJT                  ( ( uint32_t ) 0x00000008U ) /*!< Transmit jabber timeout flag */
1700     #define ETH_DMA_FLAG_TBU                  ( ( uint32_t ) 0x00000004U ) /*!< Transmit buffer unavailable flag */
1701     #define ETH_DMA_FLAG_TPS                  ( ( uint32_t ) 0x00000002U ) /*!< Transmit process stopped flag */
1702     #define ETH_DMA_FLAG_T                    ( ( uint32_t ) 0x00000001U ) /*!< Transmit flag */
1703 
1704 /**
1705  * @}
1706  */
1707 
1708 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1709  * @{
1710  */
1711     #define ETH_MAC_IT_TST     ( ( uint32_t ) 0x00000200U ) /*!< Time stamp trigger interrupt (on MAC) */
1712     #define ETH_MAC_IT_MMCT    ( ( uint32_t ) 0x00000040U ) /*!< MMC transmit interrupt */
1713     #define ETH_MAC_IT_MMCR    ( ( uint32_t ) 0x00000020U ) /*!< MMC receive interrupt */
1714     #define ETH_MAC_IT_MMC     ( ( uint32_t ) 0x00000010U ) /*!< MMC interrupt (on MAC) */
1715     #define ETH_MAC_IT_PMT     ( ( uint32_t ) 0x00000008U ) /*!< PMT interrupt (on MAC) */
1716 
1717 /**
1718  * @}
1719  */
1720 
1721 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1722  * @{
1723  */
1724     #define ETH_DMA_IT_TST    ( ( uint32_t ) 0x20000000U ) /*!< Time-stamp trigger interrupt (on DMA) */
1725     #define ETH_DMA_IT_PMT    ( ( uint32_t ) 0x10000000U ) /*!< PMT interrupt (on DMA) */
1726     #define ETH_DMA_IT_MMC    ( ( uint32_t ) 0x08000000U ) /*!< MMC interrupt (on DMA) */
1727     #define ETH_DMA_IT_NIS    ( ( uint32_t ) 0x00010000U ) /*!< Normal interrupt summary */
1728     #define ETH_DMA_IT_AIS    ( ( uint32_t ) 0x00008000U ) /*!< Abnormal interrupt summary */
1729     #define ETH_DMA_IT_ER     ( ( uint32_t ) 0x00004000U ) /*!< Early receive interrupt */
1730     #define ETH_DMA_IT_FBE    ( ( uint32_t ) 0x00002000U ) /*!< Fatal bus error interrupt */
1731     #define ETH_DMA_IT_ET     ( ( uint32_t ) 0x00000400U ) /*!< Early transmit interrupt */
1732     #define ETH_DMA_IT_RWT    ( ( uint32_t ) 0x00000200U ) /*!< Receive watchdog timeout interrupt */
1733     #define ETH_DMA_IT_RPS    ( ( uint32_t ) 0x00000100U ) /*!< Receive process stopped interrupt */
1734     #define ETH_DMA_IT_RBU    ( ( uint32_t ) 0x00000080U ) /*!< Receive buffer unavailable interrupt */
1735     #define ETH_DMA_IT_R      ( ( uint32_t ) 0x00000040U ) /*!< Receive interrupt */
1736     #define ETH_DMA_IT_TU     ( ( uint32_t ) 0x00000020U ) /*!< Underflow interrupt */
1737     #define ETH_DMA_IT_RO     ( ( uint32_t ) 0x00000010U ) /*!< Overflow interrupt */
1738     #define ETH_DMA_IT_TJT    ( ( uint32_t ) 0x00000008U ) /*!< Transmit jabber timeout interrupt */
1739     #define ETH_DMA_IT_TBU    ( ( uint32_t ) 0x00000004U ) /*!< Transmit buffer unavailable interrupt */
1740     #define ETH_DMA_IT_TPS    ( ( uint32_t ) 0x00000002U ) /*!< Transmit process stopped interrupt */
1741     #define ETH_DMA_IT_T      ( ( uint32_t ) 0x00000001U ) /*!< Transmit interrupt */
1742 
1743 /**
1744  * @}
1745  */
1746 
1747 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
1748  * @{
1749  */
1750     #define ETH_DMA_TRANSMITPROCESS_STOPPED      ( ( uint32_t ) 0x00000000U ) /*!< Stopped - Reset or Stop Tx Command issued */
1751     #define ETH_DMA_TRANSMITPROCESS_FETCHING     ( ( uint32_t ) 0x00100000U ) /*!< Running - fetching the Tx descriptor */
1752     #define ETH_DMA_TRANSMITPROCESS_WAITING      ( ( uint32_t ) 0x00200000U ) /*!< Running - waiting for status */
1753     #define ETH_DMA_TRANSMITPROCESS_READING      ( ( uint32_t ) 0x00300000U ) /*!< Running - reading the data from host memory */
1754     #define ETH_DMA_TRANSMITPROCESS_SUSPENDED    ( ( uint32_t ) 0x00600000U ) /*!< Suspended - Tx Descriptor unavailable */
1755     #define ETH_DMA_TRANSMITPROCESS_CLOSING      ( ( uint32_t ) 0x00700000U ) /*!< Running - closing Rx descriptor */
1756 
1757 /**
1758  * @}
1759  */
1760 
1761 
1762 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
1763  * @{
1764  */
1765     #define ETH_DMA_RECEIVEPROCESS_STOPPED      ( ( uint32_t ) 0x00000000U ) /*!< Stopped - Reset or Stop Rx Command issued */
1766     #define ETH_DMA_RECEIVEPROCESS_FETCHING     ( ( uint32_t ) 0x00020000U ) /*!< Running - fetching the Rx descriptor */
1767     #define ETH_DMA_RECEIVEPROCESS_WAITING      ( ( uint32_t ) 0x00060000U ) /*!< Running - waiting for packet */
1768     #define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ( ( uint32_t ) 0x00080000U ) /*!< Suspended - Rx Descriptor unavailable */
1769     #define ETH_DMA_RECEIVEPROCESS_CLOSING      ( ( uint32_t ) 0x000A0000U ) /*!< Running - closing descriptor */
1770     #define ETH_DMA_RECEIVEPROCESS_QUEUING      ( ( uint32_t ) 0x000E0000U ) /*!< Running - queuing the receive frame into host memory */
1771 
1772 /**
1773  * @}
1774  */
1775 
1776 /** @defgroup ETH_DMA_overflow ETH DMA overflow
1777  * @{
1778  */
1779     #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER         ( ( uint32_t ) 0x10000000U ) /*!< Overflow bit for FIFO overflow counter */
1780     #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER    ( ( uint32_t ) 0x00010000U ) /*!< Overflow bit for missed frame counter */
1781 
1782 /**
1783  * @}
1784  */
1785 
1786 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
1787  * @{
1788  */
1789     #define ETH_EXTI_LINE_WAKEUP    ( ( uint32_t ) 0x00080000U )   /*!< External interrupt line 19 Connected to the ETH EXTI Line */
1790 
1791 /**
1792  * @}
1793  */
1794 
1795 /**
1796  * @}
1797  */
1798 
1799 /* Exported macro ------------------------------------------------------------*/
1800 
1801 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1802  *  @brief macros to handle interrupts and specific clock configurations
1803  * @{
1804  */
1805 
1806 /** @brief Reset ETH handle state
1807  * @param  __HANDLE__: specifies the ETH handle.
1808  * @retval None
1809  */
1810     #define __HAL_ETH_RESET_HANDLE_STATE( __HANDLE__ )                            ( ( __HANDLE__ )->State = HAL_ETH_STATE_RESET )
1811 
1812 /**
1813  * @brief  Checks whether the specified Ethernet DMA Tx Desc flag is set or not.
1814  * @param  __HANDLE__: ETH Handle
1815  * @param  __FLAG__: specifies the flag of TDES0 to check.
1816  * @retval the ETH_DMATxDescFlag (SET or RESET).
1817  */
1818     #define __HAL_ETH_DMATXDESC_GET_FLAG( __HANDLE__, __FLAG__ )                  ( ( __HANDLE__ )->TxDesc->Status & ( __FLAG__ ) == ( __FLAG__ ) )
1819 
1820 /**
1821  * @brief  Checks whether the specified Ethernet DMA Rx Desc flag is set or not.
1822  * @param  __HANDLE__: ETH Handle
1823  * @param  __FLAG__: specifies the flag of RDES0 to check.
1824  * @retval the ETH_DMATxDescFlag (SET or RESET).
1825  */
1826     #define __HAL_ETH_DMARXDESC_GET_FLAG( __HANDLE__, __FLAG__ )                  ( ( __HANDLE__ )->RxDesc->Status & ( __FLAG__ ) == ( __FLAG__ ) )
1827 
1828 /**
1829  * @brief  Enables the specified DMA Rx Desc receive interrupt.
1830  * @param  __HANDLE__: ETH Handle
1831  * @retval None
1832  */
1833     #define __HAL_ETH_DMARXDESC_ENABLE_IT( __HANDLE__ )                           ( ( __HANDLE__ )->RxDesc->ControlBufferSize &= ( ~( uint32_t ) ETH_DMARXDESC_DIC ) )
1834 
1835 /**
1836  * @brief  Disables the specified DMA Rx Desc receive interrupt.
1837  * @param  __HANDLE__: ETH Handle
1838  * @retval None
1839  */
1840     #define __HAL_ETH_DMARXDESC_DISABLE_IT( __HANDLE__ )                          ( ( __HANDLE__ )->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC )
1841 
1842 /**
1843  * @brief  Set the specified DMA Rx Desc Own bit.
1844  * @param  __HANDLE__: ETH Handle
1845  * @retval None
1846  */
1847     #define __HAL_ETH_DMARXDESC_SET_OWN_BIT( __HANDLE__ )                         ( ( __HANDLE__ )->RxDesc->Status |= ETH_DMARXDESC_OWN )
1848 
1849 /**
1850  * @brief  Returns the specified Ethernet DMA Tx Desc collision count.
1851  * @param  __HANDLE__: ETH Handle
1852  * @retval The Transmit descriptor collision counter value.
1853  */
1854     #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT( __HANDLE__ )                 ( ( ( __HANDLE__ )->TxDesc->Status & ETH_DMATXDESC_CC ) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT )
1855 
1856 /**
1857  * @brief  Set the specified DMA Tx Desc Own bit.
1858  * @param  __HANDLE__: ETH Handle
1859  * @retval None
1860  */
1861     #define __HAL_ETH_DMATXDESC_SET_OWN_BIT( __HANDLE__ )                         ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_OWN )
1862 
1863 /**
1864  * @brief  Enables the specified DMA Tx Desc Transmit interrupt.
1865  * @param  __HANDLE__: ETH Handle
1866  * @retval None
1867  */
1868     #define __HAL_ETH_DMATXDESC_ENABLE_IT( __HANDLE__ )                           ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_IC )
1869 
1870 /**
1871  * @brief  Disables the specified DMA Tx Desc Transmit interrupt.
1872  * @param  __HANDLE__: ETH Handle
1873  * @retval None
1874  */
1875     #define __HAL_ETH_DMATXDESC_DISABLE_IT( __HANDLE__ )                          ( ( __HANDLE__ )->TxDesc->Status &= ~ETH_DMATXDESC_IC )
1876 
1877 /**
1878  * @brief  Selects the specified Ethernet DMA Tx Desc Checksum Insertion.
1879  * @param  __HANDLE__: ETH Handle
1880  * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
1881  *   This parameter can be one of the following values:
1882  *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
1883  *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
1884  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1885  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1886  * @retval None
1887  */
1888     #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION( __HANDLE__, __CHECKSUM__ )    ( ( __HANDLE__ )->TxDesc->Status |= ( __CHECKSUM__ ) )
1889 
1890 /**
1891  * @brief  Enables the DMA Tx Desc CRC.
1892  * @param  __HANDLE__: ETH Handle
1893  * @retval None
1894  */
1895     #define __HAL_ETH_DMATXDESC_CRC_ENABLE( __HANDLE__ )                          ( ( __HANDLE__ )->TxDesc->Status &= ~ETH_DMATXDESC_DC )
1896 
1897 /**
1898  * @brief  Disables the DMA Tx Desc CRC.
1899  * @param  __HANDLE__: ETH Handle
1900  * @retval None
1901  */
1902     #define __HAL_ETH_DMATXDESC_CRC_DISABLE( __HANDLE__ )                         ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_DC )
1903 
1904 /**
1905  * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
1906  * @param  __HANDLE__: ETH Handle
1907  * @retval None
1908  */
1909     #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE( __HANDLE__ )          ( ( __HANDLE__ )->TxDesc->Status &= ~ETH_DMATXDESC_DP )
1910 
1911 /**
1912  * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1913  * @param  __HANDLE__: ETH Handle
1914  * @retval None
1915  */
1916     #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE( __HANDLE__ )         ( ( __HANDLE__ )->TxDesc->Status |= ETH_DMATXDESC_DP )
1917 
1918 /**
1919  * @brief  Enables the specified Ethernet MAC interrupts.
1920  * @param  __HANDLE__   : ETH Handle
1921  * @param  __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be
1922  *   enabled or disabled.
1923  *   This parameter can be any combination of the following values:
1924  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1925  *     @arg ETH_MAC_IT_PMT : PMT interrupt
1926  * @retval None
1927  */
1928     #define __HAL_ETH_MAC_ENABLE_IT( __HANDLE__, __INTERRUPT__ )                  ( ( __HANDLE__ )->Instance->MACIMR |= ( __INTERRUPT__ ) )
1929 
1930 /**
1931  * @brief  Disables the specified Ethernet MAC interrupts.
1932  * @param  __HANDLE__   : ETH Handle
1933  * @param  __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be
1934  *   enabled or disabled.
1935  *   This parameter can be any combination of the following values:
1936  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1937  *     @arg ETH_MAC_IT_PMT : PMT interrupt
1938  * @retval None
1939  */
1940     #define __HAL_ETH_MAC_DISABLE_IT( __HANDLE__, __INTERRUPT__ )                 ( ( __HANDLE__ )->Instance->MACIMR &= ~( __INTERRUPT__ ) )
1941 
1942 /**
1943  * @brief  Initiate a Pause Control Frame (Full-duplex only).
1944  * @param  __HANDLE__: ETH Handle
1945  * @retval None
1946  */
1947     #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME( __HANDLE__ )                  ( ( __HANDLE__ )->Instance->MACFCR |= ETH_MACFCR_FCBBPA )
1948 
1949 /**
1950  * @brief  Checks whether the Ethernet flow control busy bit is set or not.
1951  * @param  __HANDLE__: ETH Handle
1952  * @retval The new state of flow control busy status bit (SET or RESET).
1953  */
1954     #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS( __HANDLE__ )                  ( ( ( __HANDLE__ )->Instance->MACFCR & ETH_MACFCR_FCBBPA ) == ETH_MACFCR_FCBBPA )
1955 
1956 /**
1957  * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).
1958  * @param  __HANDLE__: ETH Handle
1959  * @retval None
1960  */
1961     #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE( __HANDLE__ )               ( ( __HANDLE__ )->Instance->MACFCR |= ETH_MACFCR_FCBBPA )
1962 
1963 /**
1964  * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).
1965  * @param  __HANDLE__: ETH Handle
1966  * @retval None
1967  */
1968     #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE( __HANDLE__ )              ( ( __HANDLE__ )->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA )
1969 
1970 /**
1971  * @brief  Checks whether the specified Ethernet MAC flag is set or not.
1972  * @param  __HANDLE__: ETH Handle
1973  * @param  __FLAG__: specifies the flag to check.
1974  *   This parameter can be one of the following values:
1975  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
1976  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
1977  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag
1978  *     @arg ETH_MAC_FLAG_MMC  : MMC flag
1979  *     @arg ETH_MAC_FLAG_PMT  : PMT flag
1980  * @retval The state of Ethernet MAC flag.
1981  */
1982     #define __HAL_ETH_MAC_GET_FLAG( __HANDLE__, __FLAG__ )                        ( ( ( __HANDLE__ )->Instance->MACSR & ( __FLAG__ ) ) == ( __FLAG__ ) )
1983 
1984 /**
1985  * @brief  Enables the specified Ethernet DMA interrupts.
1986  * @param  __HANDLE__   : ETH Handle
1987  * @param  __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be
1988  *   enabled @ref ETH_DMA_Interrupts
1989  * @retval None
1990  */
1991     #define __HAL_ETH_DMA_ENABLE_IT( __HANDLE__, __INTERRUPT__ )                  ( ( __HANDLE__ )->Instance->DMAIER |= ( __INTERRUPT__ ) )
1992 
1993 /**
1994  * @brief  Disables the specified Ethernet DMA interrupts.
1995  * @param  __HANDLE__   : ETH Handle
1996  * @param  __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be
1997  *   disabled. @ref ETH_DMA_Interrupts
1998  * @retval None
1999  */
2000     #define __HAL_ETH_DMA_DISABLE_IT( __HANDLE__, __INTERRUPT__ )                 ( ( __HANDLE__ )->Instance->DMAIER &= ~( __INTERRUPT__ ) )
2001 
2002 /**
2003  * @brief  Clears the Ethernet DMA IT pending bit.
2004  * @param  __HANDLE__   : ETH Handle
2005  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
2006  * @retval None
2007  */
2008     #define __HAL_ETH_DMA_CLEAR_IT( __HANDLE__, __INTERRUPT__ )                   ( ( __HANDLE__ )->Instance->DMASR = ( __INTERRUPT__ ) )
2009 
2010 /**
2011  * @brief  Checks whether the specified Ethernet DMA flag is set or not.
2012  * @param  __HANDLE__: ETH Handle
2013  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
2014  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
2015  */
2016     #define __HAL_ETH_DMA_GET_FLAG( __HANDLE__, __FLAG__ )                        ( ( ( __HANDLE__ )->Instance->DMASR & ( __FLAG__ ) ) == ( __FLAG__ ) )
2017 
2018 /**
2019  * @brief  Checks whether the specified Ethernet DMA flag is set or not.
2020  * @param  __HANDLE__: ETH Handle
2021  * @param  __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
2022  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
2023  */
2024     #define __HAL_ETH_DMA_CLEAR_FLAG( __HANDLE__, __FLAG__ )                      ( ( __HANDLE__ )->Instance->DMASR = ( __FLAG__ ) )
2025 
2026 /**
2027  * @brief  Checks whether the specified Ethernet DMA overflow flag is set or not.
2028  * @param  __HANDLE__: ETH Handle
2029  * @param  __OVERFLOW__: specifies the DMA overflow flag to check.
2030  *   This parameter can be one of the following values:
2031  *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
2032  *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
2033  * @retval The state of Ethernet DMA overflow Flag (SET or RESET).
2034  */
2035     #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS( __HANDLE__, __OVERFLOW__ )         ( ( ( __HANDLE__ )->Instance->DMAMFBOCR & ( __OVERFLOW__ ) ) == ( __OVERFLOW__ ) )
2036 
2037 /**
2038  * @brief  Set the DMA Receive status watchdog timer register value
2039  * @param  __HANDLE__: ETH Handle
2040  * @param  __VALUE__: DMA Receive status watchdog timer register value
2041  * @retval None
2042  */
2043     #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER( __HANDLE__, __VALUE__ )         ( ( __HANDLE__ )->Instance->DMARSWTR = ( __VALUE__ ) )
2044 
2045 /**
2046  * @brief  Enables any unicast packet filtered by the MAC address
2047  *   recognition to be a wake-up frame.
2048  * @param  __HANDLE__: ETH Handle.
2049  * @retval None
2050  */
2051     #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE( __HANDLE__ )                  ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU )
2052 
2053 /**
2054  * @brief  Disables any unicast packet filtered by the MAC address
2055  *   recognition to be a wake-up frame.
2056  * @param  __HANDLE__: ETH Handle.
2057  * @retval None
2058  */
2059     #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE( __HANDLE__ )                 ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU )
2060 
2061 /**
2062  * @brief  Enables the MAC Wake-Up Frame Detection.
2063  * @param  __HANDLE__: ETH Handle.
2064  * @retval None
2065  */
2066     #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE( __HANDLE__ )                 ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE )
2067 
2068 /**
2069  * @brief  Disables the MAC Wake-Up Frame Detection.
2070  * @param  __HANDLE__: ETH Handle.
2071  * @retval None
2072  */
2073     #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE( __HANDLE__ )                ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE )
2074 
2075 /**
2076  * @brief  Enables the MAC Magic Packet Detection.
2077  * @param  __HANDLE__: ETH Handle.
2078  * @retval None
2079  */
2080     #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE( __HANDLE__ )                 ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE )
2081 
2082 /**
2083  * @brief  Disables the MAC Magic Packet Detection.
2084  * @param  __HANDLE__: ETH Handle.
2085  * @retval None
2086  */
2087     #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE( __HANDLE__ )                ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE )
2088 
2089 /**
2090  * @brief  Enables the MAC Power Down.
2091  * @param  __HANDLE__: ETH Handle
2092  * @retval None
2093  */
2094     #define __HAL_ETH_POWER_DOWN_ENABLE( __HANDLE__ )                             ( ( __HANDLE__ )->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD )
2095 
2096 /**
2097  * @brief  Disables the MAC Power Down.
2098  * @param  __HANDLE__: ETH Handle
2099  * @retval None
2100  */
2101     #define __HAL_ETH_POWER_DOWN_DISABLE( __HANDLE__ )                            ( ( __HANDLE__ )->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD )
2102 
2103 /**
2104  * @brief  Checks whether the specified Ethernet PMT flag is set or not.
2105  * @param  __HANDLE__: ETH Handle.
2106  * @param  __FLAG__: specifies the flag to check.
2107  *   This parameter can be one of the following values:
2108  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
2109  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
2110  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
2111  * @retval The new state of Ethernet PMT Flag (SET or RESET).
2112  */
2113     #define __HAL_ETH_GET_PMT_FLAG_STATUS( __HANDLE__, __FLAG__ )                 ( ( ( __HANDLE__ )->Instance->MACPMTCSR & ( __FLAG__ ) ) == ( __FLAG__ ) )
2114 
2115 /**
2116  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
2117  * @param   __HANDLE__: ETH Handle.
2118  * @retval None
2119  */
2120     #define __HAL_ETH_MMC_COUNTER_FULL_PRESET( __HANDLE__ )                       ( ( __HANDLE__ )->Instance->MMCCR |= ( ETH_MMCCR_MCFHP | ETH_MMCCR_MCP ) )
2121 
2122 /**
2123  * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
2124  * @param  __HANDLE__: ETH Handle.
2125  * @retval None
2126  */
2127     #define __HAL_ETH_MMC_COUNTER_HALF_PRESET( __HANDLE__ )   \
2128     do { ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_MCFHP; \
2129          ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_MCP; } while( 0 )
2130 
2131 /**
2132  * @brief  Enables the MMC Counter Freeze.
2133  * @param  __HANDLE__: ETH Handle.
2134  * @retval None
2135  */
2136     #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE( __HANDLE__ )           ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_MCF )
2137 
2138 /**
2139  * @brief  Disables the MMC Counter Freeze.
2140  * @param  __HANDLE__: ETH Handle.
2141  * @retval None
2142  */
2143     #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE( __HANDLE__ )          ( ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_MCF )
2144 
2145 /**
2146  * @brief  Enables the MMC Reset On Read.
2147  * @param  __HANDLE__: ETH Handle.
2148  * @retval None
2149  */
2150     #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE( __HANDLE__ )         ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_ROR )
2151 
2152 /**
2153  * @brief  Disables the MMC Reset On Read.
2154  * @param  __HANDLE__: ETH Handle.
2155  * @retval None
2156  */
2157     #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE( __HANDLE__ )        ( ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_ROR )
2158 
2159 /**
2160  * @brief  Enables the MMC Counter Stop Rollover.
2161  * @param  __HANDLE__: ETH Handle.
2162  * @retval None
2163  */
2164     #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE( __HANDLE__ )     ( ( __HANDLE__ )->Instance->MMCCR &= ~ETH_MMCCR_CSR )
2165 
2166 /**
2167  * @brief  Disables the MMC Counter Stop Rollover.
2168  * @param  __HANDLE__: ETH Handle.
2169  * @retval None
2170  */
2171     #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE( __HANDLE__ )    ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_CSR )
2172 
2173 /**
2174  * @brief  Resets the MMC Counters.
2175  * @param   __HANDLE__: ETH Handle.
2176  * @retval None
2177  */
2178     #define __HAL_ETH_MMC_COUNTERS_RESET( __HANDLE__ )                  ( ( __HANDLE__ )->Instance->MMCCR |= ETH_MMCCR_CR )
2179 
2180 /**
2181  * @brief  Enables the specified Ethernet MMC Rx interrupts.
2182  * @param   __HANDLE__: ETH Handle.
2183  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
2184  *   This parameter can be one of the following values:
2185  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
2186  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
2187  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
2188  * @retval None
2189  */
2190     #define __HAL_ETH_MMC_RX_IT_ENABLE( __HANDLE__, __INTERRUPT__ )     ( __HANDLE__ )->Instance->MMCRIMR &= ~( ( __INTERRUPT__ ) & 0xEFFFFFFF )
2191 
2192 /**
2193  * @brief  Disables the specified Ethernet MMC Rx interrupts.
2194  * @param   __HANDLE__: ETH Handle.
2195  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
2196  *   This parameter can be one of the following values:
2197  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
2198  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
2199  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
2200  * @retval None
2201  */
2202     #define __HAL_ETH_MMC_RX_IT_DISABLE( __HANDLE__, __INTERRUPT__ )    ( __HANDLE__ )->Instance->MMCRIMR |= ( ( __INTERRUPT__ ) & 0xEFFFFFFF )
2203 
2204 /**
2205  * @brief  Enables the specified Ethernet MMC Tx interrupts.
2206  * @param   __HANDLE__: ETH Handle.
2207  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
2208  *   This parameter can be one of the following values:
2209  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
2210  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2211  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2212  * @retval None
2213  */
2214     #define __HAL_ETH_MMC_TX_IT_ENABLE( __HANDLE__, __INTERRUPT__ )     ( ( __HANDLE__ )->Instance->MMCRIMR &= ~( __INTERRUPT__ ) )
2215 
2216 /**
2217  * @brief  Disables the specified Ethernet MMC Tx interrupts.
2218  * @param   __HANDLE__: ETH Handle.
2219  * @param  __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
2220  *   This parameter can be one of the following values:
2221  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
2222  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2223  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2224  * @retval None
2225  */
2226     #define __HAL_ETH_MMC_TX_IT_DISABLE( __HANDLE__, __INTERRUPT__ )    ( ( __HANDLE__ )->Instance->MMCRIMR |= ( __INTERRUPT__ ) )
2227 
2228 /**
2229  * @brief  Enables the ETH External interrupt line.
2230  * @retval None
2231  */
2232     #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()                           EXTI->IMR |= ( ETH_EXTI_LINE_WAKEUP )
2233 
2234 /**
2235  * @brief  Disables the ETH External interrupt line.
2236  * @retval None
2237  */
2238     #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()                          EXTI->IMR &= ~( ETH_EXTI_LINE_WAKEUP )
2239 
2240 /**
2241  * @brief Enable event on ETH External event line.
2242  * @retval None.
2243  */
2244     #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()                        EXTI->EMR |= ( ETH_EXTI_LINE_WAKEUP )
2245 
2246 /**
2247  * @brief Disable event on ETH External event line
2248  * @retval None.
2249  */
2250     #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT()                       EXTI->EMR &= ~( ETH_EXTI_LINE_WAKEUP )
2251 
2252 /**
2253  * @brief  Get flag of the ETH External interrupt line.
2254  * @retval None
2255  */
2256     #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()                            EXTI->PR & ( ETH_EXTI_LINE_WAKEUP )
2257 
2258 /**
2259  * @brief  Clear flag of the ETH External interrupt line.
2260  * @retval None
2261  */
2262     #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()                          EXTI->PR = ( ETH_EXTI_LINE_WAKEUP )
2263 
2264 /**
2265  * @brief  Enables rising edge trigger to the ETH External interrupt line.
2266  * @retval None
2267  */
2268     #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()          EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2269 
2270 /**
2271  * @brief  Disables the rising edge trigger to the ETH External interrupt line.
2272  * @retval None
2273  */
2274     #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()         EXTI->RTSR &= ~( ETH_EXTI_LINE_WAKEUP )
2275 
2276 /**
2277  * @brief  Enables falling edge trigger to the ETH External interrupt line.
2278  * @retval None
2279  */
2280     #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()         EXTI->FTSR |= ( ETH_EXTI_LINE_WAKEUP )
2281 
2282 /**
2283  * @brief  Disables falling edge trigger to the ETH External interrupt line.
2284  * @retval None
2285  */
2286     #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()        EXTI->FTSR &= ~( ETH_EXTI_LINE_WAKEUP )
2287 
2288 /**
2289  * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.
2290  * @retval None
2291  */
2292     #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() \
2293     EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;                          \
2294     EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
2295 
2296 /**
2297  * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.
2298  * @retval None
2299  */
2300     #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() \
2301     EXTI->RTSR &= ~( ETH_EXTI_LINE_WAKEUP );                      \
2302     EXTI->FTSR &= ~( ETH_EXTI_LINE_WAKEUP )
2303 
2304 /**
2305  * @brief Generate a Software interrupt on selected EXTI line.
2306  * @retval None.
2307  */
2308     #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()    EXTI->SWIER |= ETH_EXTI_LINE_WAKEUP
2309 
2310 /**
2311  * @}
2312  */
2313 /* Exported functions --------------------------------------------------------*/
2314 
2315 /** @addtogroup ETH_Exported_Functions
2316  * @{
2317  */
2318 
2319 /* Initialization and de-initialization functions  ****************************/
2320 
2321 /** @addtogroup ETH_Exported_Functions_Group1
2322  * @{
2323  */
2324     HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef * heth );
2325     HAL_StatusTypeDef HAL_ETH_DeInit( ETH_HandleTypeDef * heth );
2326     void HAL_ETH_MspInit( ETH_HandleTypeDef * heth );
2327     void HAL_ETH_MspDeInit( ETH_HandleTypeDef * heth );
2328     HAL_StatusTypeDef HAL_ETH_DMATxDescListInit( ETH_HandleTypeDef * heth,
2329                                                  ETH_DMADescTypeDef * DMATxDescTab,
2330                                                  uint8_t * TxBuff,
2331                                                  uint32_t TxBuffCount );
2332     HAL_StatusTypeDef HAL_ETH_DMARxDescListInit( ETH_HandleTypeDef * heth,
2333                                                  ETH_DMADescTypeDef * DMARxDescTab,
2334                                                  uint8_t * RxBuff,
2335                                                  uint32_t RxBuffCount );
2336 
2337 /**
2338  * @}
2339  */
2340 /* IO operation functions  ****************************************************/
2341 
2342 /** @addtogroup ETH_Exported_Functions_Group2
2343  * @{
2344  */
2345     HAL_StatusTypeDef HAL_ETH_TransmitFrame( ETH_HandleTypeDef * heth,
2346                                              uint32_t FrameLength );
2347     HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef * heth );
2348 /* Communication with PHY functions*/
2349     HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef * heth,
2350                                                uint16_t PHYReg,
2351                                                uint32_t * RegValue );
2352     HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef * heth,
2353                                                 uint16_t PHYReg,
2354                                                 uint32_t RegValue );
2355 /* Non-Blocking mode: Interrupt */
2356     HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef * heth );
2357     void HAL_ETH_IRQHandler( ETH_HandleTypeDef * heth );
2358 /* Callback in non blocking modes (Interrupt) */
2359     void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth );
2360     void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth );
2361     void HAL_ETH_ErrorCallback( ETH_HandleTypeDef * heth );
2362 
2363 /**
2364  * @}
2365  */
2366 
2367 /* Peripheral Control functions  **********************************************/
2368 
2369 /** @addtogroup ETH_Exported_Functions_Group3
2370  * @{
2371  */
2372 
2373     HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef * heth );
2374     HAL_StatusTypeDef HAL_ETH_Stop( ETH_HandleTypeDef * heth );
2375     HAL_StatusTypeDef HAL_ETH_ConfigMAC( ETH_HandleTypeDef * heth,
2376                                          ETH_MACInitTypeDef * macconf );
2377     HAL_StatusTypeDef HAL_ETH_ConfigDMA( ETH_HandleTypeDef * heth,
2378                                          ETH_DMAInitTypeDef * dmaconf );
2379 
2380 /**
2381  * @}
2382  */
2383 
2384 /* Peripheral State functions  ************************************************/
2385 
2386 /** @addtogroup ETH_Exported_Functions_Group4
2387  * @{
2388  */
2389     HAL_ETH_StateTypeDef HAL_ETH_GetState( ETH_HandleTypeDef * heth );
2390 
2391 /**
2392  * @}
2393  */
2394 
2395 /**
2396  * @}
2397  */
2398 
2399 /**
2400  * @}
2401  */
2402 
2403 /**
2404  * @}
2405  */
2406     #ifdef __cplusplus
2407         }
2408     #endif
2409 
2410 #endif /* __STM32Fxx_HAL_ETH_H */
2411 
2412 
2413 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2414