1 /** 2 ****************************************************************************** 3 * @file stm32hxx_hal_eth.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32Hxx_HAL_ETH_H 22 #define STM32Hxx_HAL_ETH_H 23 24 #define STM32H7xx_HAL_ETH_H 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32h7xx_hal_def.h" 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #if defined( ETH ) 34 35 /** @addtogroup STM32H7xx_HAL_Driver 36 * @{ 37 */ 38 39 /** @addtogroup ETH 40 * @{ 41 */ 42 43 /* Exported types ------------------------------------------------------------*/ 44 #ifndef ETH_TX_DESC_CNT 45 #error Please define ETH_TX_DESC_CNT in your stm32h7xx_hal_conf.h 46 #endif 47 48 #ifndef ETH_RX_DESC_CNT 49 #error Please define ETH_RX_DESC_CNT in your stm32h7xx_hal_conf.h 50 #endif 51 52 /*********************** Descriptors struct def section ************************/ 53 54 /** @defgroup ETH_Exported_Types ETH Exported Types 55 * @{ 56 */ 57 struct xErrorFields 58 { 59 uint16_t 60 ERR_IHE : 1, /* IP Header Error */ 61 ERR_DB : 1, /* Deferred Bit */ 62 ERR_Umderflow : 1, /* Underflow Error */ 63 ERR_ExcDefer : 1, /* Excessive Deferral */ 64 ERR_CC : 4, /* Collision count. */ 65 ERR_EC : 1, /* Excessive Collision */ 66 ERR_LC : 1, /* Late collision. */ 67 ERR_NC : 1, /* No carrier. */ 68 ERR_LoC : 1, /* Loss of Carrier: carrier lost during transmission */ 69 ERR_PCE : 1, /* Payload Checksum Error */ 70 ERR_FF : 1, /* Packet Flushed: DMA/MTL flushed the packet due to SW flush */ 71 ERR_JT : 1, /* Jabber Timeout */ 72 ERR_SUMMARY : 1; 73 } 74 __attribute__( ( packed ) ); 75 76 /** 77 * @brief ETH DMA Descriptor structure definition 78 */ 79 typedef struct 80 { 81 union 82 { 83 __IO uint32_t DESC0; /* The buffer */ 84 uint32_t Buffer_1____; 85 }; 86 union 87 { 88 __IO uint32_t DESC1; 89 uint32_t Buffer_2____; 90 }; 91 union 92 { 93 __IO uint32_t DESC2; /* Buffer 1 length (0x00003FFFU) Buffer 2 Length (0x3FFF0000) */ 94 struct 95 { 96 unsigned 97 Buff1_Length : 14, /* Buffer 1 Length */ 98 VTIR________ : 2, /* VLAN Tag Insertion or Replacement mask */ 99 Buff2_Length : 14, /* Buffer 2 Length */ 100 TTSE________ : 1, /* Transmit Timestamp Enable */ 101 IOC_________ : 1; /* Interrupt on Completion */ 102 }; 103 }; 104 union 105 { 106 __IO uint32_t DESC3; /* bit 31 is the OWN (by DMA) bit */ 107 struct 108 { 109 struct xErrorFields ERR_FIELDS; 110 struct 111 { 112 uint16_t 113 114 Reserved_1__ : 1, 115 TIMESTAMP___ : 1, /*!< Tx Timestamp Status */ 116 Reserved_3__ : 10, 117 LAST_DESC___ : 1, /*!< Last Descriptor */ 118 FIRST_DESC__ : 1, /*!< First Descriptor */ 119 STATUS_CTX__ : 1, /*!< Context Type */ 120 OWN_________ : 1; 121 } __attribute__( ( packed ) ); 122 }; 123 }; 124 uint32_t BackupAddr0; /* used to store rx buffer 1 address */ 125 uint32_t BackupAddr1; /* used to store rx buffer 2 address */ 126 } ETH_DMADescTypeDef; 127 128 /* 129 * Channel status register ( see field DMACSR, or "ETH_DMACSR". 130 */ 131 typedef struct 132 { 133 union 134 { 135 uint32_t ulValue; 136 struct 137 { 138 uint32_t 139 TI_Transmit_Interrupt__________ : 1, 140 TPS_Transmit_Process_Stopped___ : 1, 141 TBU_Transmit_Buffer_Unavailable : 1, 142 R_0 : 3, 143 RI_Receive_Interrupt___________ : 1, 144 RBU_Receive_Buffer_Unavailable_ : 1, 145 RPS_Receive_Process_Stopped____ : 1, 146 RWT_Receive_Watchdog_Timeout___ : 1, 147 ETI_Early_Transmit_Interrupt___ : 1, 148 ERI_Early_Receive_Interrupt____ : 1, 149 FBE_Fatal_Bus_Error____________ : 1, 150 CDE_Context_Descriptor_Error___ : 1, 151 AIS_Abnormal_Interrupt_Summary_ : 1, 152 NIS_Normal_Interrupt_Summary___ : 1, 153 154 REB_0_Error_during_read_transfer_when_1__________ : 1, 155 REB_1_Error_during_descriptor_access_when_1______ : 1, 156 REB_2_Error_during_data_transfer_by_Rx_DMA_when_1 : 1, 157 158 TEB_0_Error_during_read_transfer_when_1__________ : 1, 159 TEB_1_Error_during_descriptor_access_when_1______ : 1, 160 TEB_2_Error_during_data_transfer_by_Tx_DMA_when_1 : 1, 161 162 R_1 : 10; 163 }; 164 }; 165 } IntStatus_t; 166 167 /** 168 * 169 */ 170 171 /** 172 * @brief ETH Buffers List structure definition 173 */ 174 typedef struct __ETH_BufferTypeDef 175 { 176 uint8_t * buffer; /*<! buffer address */ 177 178 uint32_t len; /*<! buffer length */ 179 180 struct __ETH_BufferTypeDef * next; /*<! Pointer to the next buffer in the list */ 181 } ETH_BufferTypeDef; 182 183 /** 184 * 185 */ 186 187 /** 188 * @brief DMA Transmit Descriptors Wrapper structure definition 189 */ 190 typedef struct 191 { 192 uint32_t TxDesc[ ETH_TX_DESC_CNT ]; /*<! Tx DMA descriptors addresses */ 193 194 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */ 195 196 uint32_t TailTxDesc; /*<! Next TX packet to clean up the buffer */ 197 } ETH_TxDescListTypeDef; 198 199 /** 200 * 201 */ 202 203 /** 204 * @brief Transmit Packet Configuration structure definition 205 */ 206 typedef struct 207 { 208 uint32_t Attributes; /*!< Tx packet HW features capabilities. 209 * This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/ 210 211 uint32_t Length; /*!< Total packet length */ 212 213 ETH_BufferTypeDef * TxBuffer; /*!< Tx buffers pointers */ 214 215 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control. 216 * This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */ 217 218 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control. 219 * This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */ 220 221 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control. 222 * This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */ 223 224 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 225 * This parameter can be a value from 0x0 to 0x3FFF */ 226 227 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled. 228 * This parameter can be a value from 0x0 to 0x3FFFF */ 229 230 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled. 231 * This parameter can be a value from 0x5 to 0xF */ 232 233 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled. 234 * This parameter can be a value from 0x0 to 0xFFFF*/ 235 236 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 237 * This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */ 238 239 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled. 240 * This parameter can be a value from 0x0 to 0x3FFFF */ 241 242 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 243 * This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */ 244 } ETH_TxPacketConfig; 245 246 /** 247 * 248 */ 249 250 /** 251 * @brief DMA Receive Descriptors Wrapper structure definition 252 */ 253 typedef struct 254 { 255 uint32_t RxDesc[ ETH_RX_DESC_CNT ]; /*<! Rx DMA descriptors addresses. */ 256 257 uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */ 258 259 uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */ 260 261 uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */ 262 263 uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet. 264 * If 0 no context descriptor is present in last received packet. */ 265 266 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt. 267 * If 0, DMA will not generate the Rx complete interrupt. */ 268 } ETH_RxDescListTypeDef; 269 270 /** 271 * 272 */ 273 274 /** 275 * @brief Received Packet Information structure definition 276 */ 277 typedef struct 278 { 279 uint32_t SegmentCnt; /*<! Number of Rx Descriptors */ 280 281 uint32_t VlanTag; /*<! Vlan Tag value */ 282 283 uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */ 284 285 uint32_t Checksum; /*<! Rx Checksum status. 286 * This parameter can be a value of @ref ETH_Rx_Checksum_Status */ 287 288 uint32_t HeaderType; /*<! IP header type. 289 * This parameter can be a value of @ref ETH_Rx_IP_Header_Type */ 290 291 uint32_t PayloadType; /*<! Payload type. 292 * This parameter can be a value of @ref ETH_Rx_Payload_Type */ 293 294 uint32_t MacFilterStatus; /*<! MAC filter status. 295 * This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */ 296 297 uint32_t L3FilterStatus; /*<! L3 filter status 298 * This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */ 299 300 uint32_t L4FilterStatus; /*<! L4 filter status 301 * This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */ 302 303 uint32_t ErrorCode; /*<! Rx error code 304 * This parameter can be a combination of @ref ETH_Rx_Error_Code */ 305 } ETH_RxPacketInfo; 306 307 /** 308 * 309 */ 310 311 /** 312 * @brief ETH MAC Configuration Structure definition 313 */ 314 typedef struct 315 { 316 uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control. 317 * This parameter can be a value of @ref ETH_Source_Addr_Control */ 318 319 FunctionalState ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */ 320 321 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission. 322 * This parameter can be a value of @ref ETH_Inter_Packet_Gap */ 323 324 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */ 325 326 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 327 328 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/ 329 330 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/ 331 332 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path 333 * When enabled, the MAC allows no more then 2048 bytes to be received. 334 * When disabled, the MAC can receive up to 16384 bytes. */ 335 336 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path 337 * When enabled, the MAC allows no more then 2048 bytes to be sent. 338 * When disabled, the MAC can send up to 16384 bytes. */ 339 340 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet 341 * When enabled, the MAC allows jumbo packets of 9,018 bytes 342 * without reporting a giant packet error */ 343 344 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 345 * This parameter can be a value of @ref ETH_Speed */ 346 347 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 348 * This parameter can be a value of @ref ETH_Duplex_Mode */ 349 350 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */ 351 352 FunctionalState CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */ 353 354 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */ 355 356 FunctionalState CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */ 357 358 FunctionalState RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/ 359 360 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 361 * This parameter can be a value of @ref ETH_Back_Off_Limit */ 362 363 FunctionalState DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */ 364 365 uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode). 366 * This parameter can be a value of @ref ETH_Preamble_Length */ 367 368 FunctionalState UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */ 369 370 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */ 371 372 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */ 373 374 uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 375 * greater than the value programmed in this field in units of bytes 376 * This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/ 377 378 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */ 379 380 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission. 381 * This parameter can be a value from 0x0 to 0xFF */ 382 383 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/ 384 385 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet 386 * This parameter can be a value of @ref ETH_Watchdog_Timeout */ 387 388 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 389 * This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 390 391 FunctionalState ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/ 392 393 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet. 394 * This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 395 396 FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode 397 * or the MAC back pressure operation in Half Duplex mode */ 398 399 FunctionalState UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */ 400 401 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet 402 * and disables its transmitter for a specified (Pause) time */ 403 404 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode. 405 * This parameter can be a value of @ref ETH_Transmit_Mode */ 406 407 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode. 408 * This parameter can be a value of @ref ETH_Receive_Mode */ 409 410 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 411 412 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */ 413 414 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/ 415 } ETH_MACConfigTypeDef; 416 417 /** 418 * 419 */ 420 421 /** 422 * @brief ETH DMA Configuration Structure definition 423 */ 424 typedef struct 425 { 426 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx 427 * This parameter can be a value of @ref ETH_DMA_Arbitration */ 428 429 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned 430 * burst transfers on Read and Write channels */ 431 432 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. 433 * This parameter can be a value of @ref ETH_Burst_Mode */ 434 435 FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats 436 * of any initiated burst transfer with INCRx and SINGLE transfers. */ 437 438 FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */ 439 440 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 441 * This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 442 443 FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second 444 * Packet of Transmit data even before obtaining the status for the first one. */ 445 446 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 447 * This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 448 449 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */ 450 451 FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */ 452 453 uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet 454 * This parameter can be a value from 0x40 to 0x3FFF */ 455 } ETH_DMAConfigTypeDef; 456 457 /** 458 * 459 */ 460 461 /** 462 * @brief HAL ETH Media Interfaces enum definition 463 */ 464 typedef enum 465 { 466 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */ 467 HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */ 468 } ETH_MediaInterfaceTypeDef; 469 470 /** 471 * 472 */ 473 474 /** 475 * @brief ETH Init Structure definition 476 */ 477 typedef struct 478 { 479 uint8_t * MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 480 481 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */ 482 483 ETH_DMADescTypeDef * TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */ 484 485 ETH_DMADescTypeDef * RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */ 486 487 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */ 488 } ETH_InitTypeDef; 489 490 /** 491 * 492 */ 493 494 /** 495 * @brief HAL State structures definition 496 */ 497 typedef uint32_t HAL_ETH_StateTypeDef; 498 499 /** 500 * 501 */ 502 503 /** 504 * @brief ETH Handle Structure definition 505 */ 506 #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) 507 typedef struct __ETH_HandleTypeDef 508 #else 509 typedef struct 510 #endif 511 { 512 ETH_TypeDef * Instance; /*!< Register base address */ 513 514 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 515 516 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list 517 * addresses and current descriptor index */ 518 519 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list 520 * addresses and current descriptor index */ 521 522 HAL_LockTypeDef Lock; /*!< Locking object */ 523 524 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management 525 * and also related to Tx operations. 526 * This parameter can be a value of @ref HAL_ETH_StateTypeDef */ 527 528 __IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations. 529 * This parameter can be a value of @ref HAL_ETH_StateTypeDef */ 530 531 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine 532 * This parameter can be a value of of @ref ETH_Error_Code */ 533 534 __IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs 535 * This parameter can be a combination of @ref ETH_DMA_Status_Flags */ 536 537 __IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs 538 * This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */ 539 540 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode 541 * This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */ 542 543 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs. 544 * This parameter can be a value of @ref ETHEx_LPI_Event */ 545 546 #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) 547 void ( * TxCpltCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH Tx Complete Callback */ 548 void ( * RxCpltCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH Rx Complete Callback */ 549 void ( * DMAErrorCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH DMA Error Callback */ 550 void ( * MACErrorCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH MAC Error Callback */ 551 void ( * PMTCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH Power Management Callback */ 552 void ( * EEECallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH EEE Callback */ 553 void ( * WakeUpCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH Wake UP Callback */ 554 555 void ( * MspInitCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH Msp Init callback */ 556 void ( * MspDeInitCallback )( struct __ETH_HandleTypeDef * heth ); /*!< ETH Msp DeInit callback */ 557 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 558 } ETH_HandleTypeDef; 559 560 /** 561 * 562 */ 563 564 #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) 565 566 /** 567 * @brief HAL ETH Callback ID enumeration definition 568 */ 569 typedef enum 570 { 571 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 572 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 573 574 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 575 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 576 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 577 HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /*!< ETH MAC Error Callback ID */ 578 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ 579 HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */ 580 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ 581 } HAL_ETH_CallbackIDTypeDef; 582 583 /** 584 * @brief HAL ETH Callback pointer definition 585 */ 586 typedef void (* pETH_CallbackTypeDef)( ETH_HandleTypeDef * heth ); /*!< pointer to an ETH callback function */ 587 588 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 589 590 /** 591 * @brief ETH MAC filter structure definition 592 */ 593 typedef struct 594 { 595 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */ 596 597 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */ 598 599 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */ 600 601 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */ 602 603 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */ 604 605 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */ 606 607 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */ 608 609 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */ 610 611 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */ 612 613 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */ 614 615 uint32_t ControlPacketsFilter; /*!< Set the control packets filter 616 * This parameter can be a value of @ref ETH_Control_Packets_Filter */ 617 } ETH_MACFilterConfigTypeDef; 618 619 /** 620 * 621 */ 622 623 /** 624 * @brief ETH Power Down structure definition 625 */ 626 typedef struct 627 { 628 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */ 629 630 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */ 631 632 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */ 633 634 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */ 635 } ETH_PowerDownConfigTypeDef; 636 637 /** 638 * 639 */ 640 641 /** 642 * @} 643 */ 644 645 /* Exported constants --------------------------------------------------------*/ 646 647 /** @defgroup ETH_Exported_Constants ETH Exported Constants 648 * @{ 649 */ 650 651 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition 652 * @{ 653 */ 654 655 /* 656 * DMA Tx Normal Desciptor Read Format 657 * ----------------------------------------------------------------------------------------------- 658 * TDES0 | Buffer1 or Header Address [31:0] | 659 * ----------------------------------------------------------------------------------------------- 660 * TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 661 * ----------------------------------------------------------------------------------------------- 662 * TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] | 663 * ----------------------------------------------------------------------------------------------- 664 * TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 665 * ----------------------------------------------------------------------------------------------- 666 */ 667 668 /** 669 * @brief Bit definition of TDES0 RF register 670 */ 671 #define ETH_DMATXNDESCRF_B1AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Transmit Packet Timestamp Low */ 672 673 /** 674 * @brief Bit definition of TDES1 RF register 675 */ 676 #define ETH_DMATXNDESCRF_B2AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Transmit Packet Timestamp High */ 677 678 /** 679 * @brief Bit definition of TDES2 RF register 680 */ 681 #define ETH_DMATXNDESCRF_IOC ( ( uint32_t ) 0x80000000U ) /*!< Interrupt on Completion */ 682 #define ETH_DMATXNDESCRF_TTSE ( ( uint32_t ) 0x40000000U ) /*!< Transmit Timestamp Enable */ 683 #define ETH_DMATXNDESCRF_B2L ( ( uint32_t ) 0x3FFF0000U ) /*!< Buffer 2 Length */ 684 #define ETH_DMATXNDESCRF_VTIR ( ( uint32_t ) 0x0000C000U ) /*!< VLAN Tag Insertion or Replacement mask */ 685 #define ETH_DMATXNDESCRF_VTIR_DISABLE ( ( uint32_t ) 0x00000000U ) /*!< Do not add a VLAN tag. */ 686 #define ETH_DMATXNDESCRF_VTIR_REMOVE ( ( uint32_t ) 0x00004000U ) /*!< Remove the VLAN tag from the packets before transmission. */ 687 #define ETH_DMATXNDESCRF_VTIR_INSERT ( ( uint32_t ) 0x00008000U ) /*!< Insert a VLAN tag. */ 688 #define ETH_DMATXNDESCRF_VTIR_REPLACE ( ( uint32_t ) 0x0000C000U ) /*!< Replace the VLAN tag. */ 689 #define ETH_DMATXNDESCRF_B1L ( ( uint32_t ) 0x00003FFFU ) /*!< Buffer 1 Length */ 690 #define ETH_DMATXNDESCRF_HL ( ( uint32_t ) 0x000003FFU ) /*!< Header Length */ 691 692 /** 693 * @brief Bit definition of TDES3 RF register 694 */ 695 #define ETH_DMATXNDESCRF_OWN ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine */ 696 #define ETH_DMATXNDESCRF_CTXT ( ( uint32_t ) 0x40000000U ) /*!< Context Type */ 697 #define ETH_DMATXNDESCRF_FD ( ( uint32_t ) 0x20000000U ) /*!< First Descriptor */ 698 #define ETH_DMATXNDESCRF_LD ( ( uint32_t ) 0x10000000U ) /*!< Last Descriptor */ 699 #define ETH_DMATXNDESCRF_CPC ( ( uint32_t ) 0x0C000000U ) /*!< CRC Pad Control mask */ 700 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ( ( uint32_t ) 0x00000000U ) /*!< CRC Pad Control: CRC and Pad Insertion */ 701 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT ( ( uint32_t ) 0x04000000U ) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */ 702 #define ETH_DMATXNDESCRF_CPC_DISABLE ( ( uint32_t ) 0x08000000U ) /*!< CRC Pad Control: Disable CRC Insertion */ 703 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ( ( uint32_t ) 0x0C000000U ) /*!< CRC Pad Control: CRC Replacement */ 704 #define ETH_DMATXNDESCRF_SAIC ( ( uint32_t ) 0x03800000U ) /*!< SA Insertion Control mask*/ 705 #define ETH_DMATXNDESCRF_SAIC_DISABLE ( ( uint32_t ) 0x00000000U ) /*!< SA Insertion Control: Do not include the source address */ 706 #define ETH_DMATXNDESCRF_SAIC_INSERT ( ( uint32_t ) 0x00800000U ) /*!< SA Insertion Control: Include or insert the source address */ 707 #define ETH_DMATXNDESCRF_SAIC_REPLACE ( ( uint32_t ) 0x01000000U ) /*!< SA Insertion Control: Replace the source address */ 708 #define ETH_DMATXNDESCRF_THL ( ( uint32_t ) 0x00780000U ) /*!< TCP Header Length */ 709 #define ETH_DMATXNDESCRF_TSE ( ( uint32_t ) 0x00040000U ) /*!< TCP segmentation enable */ 710 #define ETH_DMATXNDESCRF_CIC ( ( uint32_t ) 0x00030000U ) /*!< Checksum Insertion Control: 4 cases */ 711 #define ETH_DMATXNDESCRF_CIC_DISABLE ( ( uint32_t ) 0x00000000U ) /*!< Do Nothing: Checksum Engine is disabled */ 712 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ( ( uint32_t ) 0x00010000U ) /*!< Only IP header checksum calculation and insertion are enabled. */ 713 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ( ( uint32_t ) 0x00020000U ) /*!< IP header checksum and payload checksum calculation and insertion are 714 * enabled, but pseudo header checksum is not calculated in hardware */ 715 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ( ( uint32_t ) 0x00030000U ) /*!< IP Header checksum and payload checksum calculation and insertion are 716 * enabled, and pseudo header checksum is calculated in hardware. */ 717 #define ETH_DMATXNDESCRF_TPL ( ( uint32_t ) 0x0003FFFFU ) /*!< TCP Payload Length */ 718 #define ETH_DMATXNDESCRF_FL ( ( uint32_t ) 0x00007FFFU ) /*!< Transmit End of Ring */ 719 720 /* 721 * DMA Tx Normal Descriptor Write Back Format 722 * ----------------------------------------------------------------------------------------------- 723 * TDES0 | Timestamp Low | 724 * ----------------------------------------------------------------------------------------------- 725 * TDES1 | Timestamp High | 726 * ----------------------------------------------------------------------------------------------- 727 * TDES2 | Reserved[31:0] | 728 * ----------------------------------------------------------------------------------------------- 729 * TDES3 | OWN(31) | Status[30:0] | 730 * ----------------------------------------------------------------------------------------------- 731 */ 732 733 /** 734 * @brief Bit definition of TDES0 WBF register 735 */ 736 #define ETH_DMATXNDESCWBF_TTSL ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */ 737 738 /** 739 * @brief Bit definition of TDES1 WBF register 740 */ 741 #define ETH_DMATXNDESCWBF_TTSH ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer2 Address Pointer */ 742 743 /** 744 * @brief Bit definition of TDES3 WBF register 745 */ 746 #define ETH_DMATXNDESCWBF_OWN ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine */ 747 #define ETH_DMATXNDESCWBF_CTXT ( ( uint32_t ) 0x40000000U ) /*!< Context Type */ 748 #define ETH_DMATXNDESCWBF_FD ( ( uint32_t ) 0x20000000U ) /*!< First Descriptor */ 749 #define ETH_DMATXNDESCWBF_LD ( ( uint32_t ) 0x10000000U ) /*!< Last Descriptor */ 750 #define ETH_DMATXNDESCWBF_TTSS ( ( uint32_t ) 0x00020000U ) /*!< Tx Timestamp Status */ 751 #define ETH_DMATXNDESCWBF_DP ( ( uint32_t ) 0x04000000U ) /*!< Disable Padding */ 752 #define ETH_DMATXNDESCWBF_TTSE ( ( uint32_t ) 0x02000000U ) /*!< Transmit Timestamp Enable */ 753 #define ETH_DMATXNDESCWBF_ES ( ( uint32_t ) 0x00008000U ) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */ 754 #define ETH_DMATXNDESCWBF_JT ( ( uint32_t ) 0x00004000U ) /*!< Jabber Timeout */ 755 #define ETH_DMATXNDESCWBF_FF ( ( uint32_t ) 0x00002000U ) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */ 756 #define ETH_DMATXNDESCWBF_PCE ( ( uint32_t ) 0x00001000U ) /*!< Payload Checksum Error */ 757 #define ETH_DMATXNDESCWBF_LCA ( ( uint32_t ) 0x00000800U ) /*!< Loss of Carrier: carrier lost during transmission */ 758 #define ETH_DMATXNDESCWBF_NC ( ( uint32_t ) 0x00000400U ) /*!< No Carrier: no carrier signal from the transceiver */ 759 #define ETH_DMATXNDESCWBF_LCO ( ( uint32_t ) 0x00000200U ) /*!< Late Collision: transmission aborted due to collision */ 760 #define ETH_DMATXNDESCWBF_EC ( ( uint32_t ) 0x00000100U ) /*!< Excessive Collision: transmission aborted after 16 collisions */ 761 #define ETH_DMATXNDESCWBF_CC ( ( uint32_t ) 0x000000F0U ) /*!< Collision Count */ 762 #define ETH_DMATXNDESCWBF_ED ( ( uint32_t ) 0x00000008U ) /*!< Excessive Deferral */ 763 #define ETH_DMATXNDESCWBF_UF ( ( uint32_t ) 0x00000004U ) /*!< Underflow Error: late data arrival from the memory */ 764 #define ETH_DMATXNDESCWBF_DB ( ( uint32_t ) 0x00000002U ) /*!< Deferred Bit */ 765 #define ETH_DMATXNDESCWBF_IHE ( ( uint32_t ) 0x00000004U ) /*!< IP Header Error */ 766 767 768 /* 769 * DMA Tx Context Desciptor 770 * ----------------------------------------------------------------------------------------------- 771 * TDES0 | Timestamp Low | 772 * ----------------------------------------------------------------------------------------------- 773 * TDES1 | Timestamp High | 774 * ----------------------------------------------------------------------------------------------- 775 * TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] | 776 * ----------------------------------------------------------------------------------------------- 777 * TDES3 | OWN(31) | Status[30:0] | 778 * ----------------------------------------------------------------------------------------------- 779 */ 780 781 /** 782 * @brief Bit definition of Tx context descriptor register 0 783 */ 784 #define ETH_DMATXCDESC_TTSL ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Transmit Packet Timestamp Low */ 785 786 /** 787 * @brief Bit definition of Tx context descriptor register 1 788 */ 789 #define ETH_DMATXCDESC_TTSH ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Transmit Packet Timestamp High */ 790 791 /** 792 * @brief Bit definition of Tx context descriptor register 2 793 */ 794 #define ETH_DMATXCDESC_IVT ( ( uint32_t ) 0xFFFF0000U ) /*!< Inner VLAN Tag */ 795 #define ETH_DMATXCDESC_MSS ( ( uint32_t ) 0x00003FFFU ) /*!< Maximum Segment Size */ 796 797 /** 798 * @brief Bit definition of Tx context descriptor register 3 799 */ 800 #define ETH_DMATXCDESC_OWN ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine */ 801 #define ETH_DMATXCDESC_CTXT ( ( uint32_t ) 0x40000000U ) /*!< Context Type */ 802 #define ETH_DMATXCDESC_OSTC ( ( uint32_t ) 0x08000000U ) /*!< One-Step Timestamp Correction Enable */ 803 #define ETH_DMATXCDESC_TCMSSV ( ( uint32_t ) 0x04000000U ) /*!< One-Step Timestamp Correction Input or MSS Valid */ 804 #define ETH_DMATXCDESC_CDE ( ( uint32_t ) 0x00800000U ) /*!< Context Descriptor Error */ 805 #define ETH_DMATXCDESC_IVTIR ( ( uint32_t ) 0x000C0000U ) /*!< Inner VLAN Tag Insert or Replace Mask */ 806 #define ETH_DMATXCDESC_IVTIR_DISABLE ( ( uint32_t ) 0x00000000U ) /*!< Do not add the inner VLAN tag. */ 807 #define ETH_DMATXCDESC_IVTIR_REMOVE ( ( uint32_t ) 0x00040000U ) /*!< Remove the inner VLAN tag from the packets before transmission. */ 808 #define ETH_DMATXCDESC_IVTIR_INSERT ( ( uint32_t ) 0x00080000U ) /*!< Insert the inner VLAN tag. */ 809 #define ETH_DMATXCDESC_IVTIR_REPLACE ( ( uint32_t ) 0x000C0000U ) /*!< Replace the inner VLAN tag. */ 810 #define ETH_DMATXCDESC_IVLTV ( ( uint32_t ) 0x00020000U ) /*!< Inner VLAN Tag Valid */ 811 #define ETH_DMATXCDESC_VLTV ( ( uint32_t ) 0x00010000U ) /*!< VLAN Tag Valid */ 812 #define ETH_DMATXCDESC_VT ( ( uint32_t ) 0x0000FFFFU ) /*!< VLAN Tag */ 813 814 /** 815 * @} 816 */ 817 818 819 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition 820 * @{ 821 */ 822 823 /* 824 * DMA Rx Normal Descriptor read format 825 * ----------------------------------------------------------------------------------------------------------- 826 * RDES0 | Buffer1 or Header Address [31:0] | 827 * ----------------------------------------------------------------------------------------------------------- 828 * RDES1 | Reserved | 829 * ----------------------------------------------------------------------------------------------------------- 830 * RDES2 | Payload or Buffer2 Address[31:0] | 831 * ----------------------------------------------------------------------------------------------------------- 832 * RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] | 833 * ----------------------------------------------------------------------------------------------------------- 834 */ 835 836 /** 837 * @brief Bit definition of Rx normal descriptor register 0 read format 838 */ 839 #define ETH_DMARXNDESCRF_BUF1AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Header or Buffer 1 Address Pointer */ 840 841 /** 842 * @brief Bit definition of Rx normal descriptor register 2 read format 843 */ 844 #define ETH_DMARXNDESCRF_BUF2AP ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Buffer 2 Address Pointer */ 845 846 /** 847 * @brief Bit definition of Rx normal descriptor register 3 read format 848 */ 849 #define ETH_DMARXNDESCRF_OWN ( ( uint32_t ) 0x80000000U ) /*!< OWN bit: descriptor is owned by DMA engine */ 850 #define ETH_DMARXNDESCRF_IOC ( ( uint32_t ) 0x40000000U ) /*!< Interrupt Enabled on Completion */ 851 #define ETH_DMARXNDESCRF_BUF2V ( ( uint32_t ) 0x02000000U ) /*!< Buffer 2 Address Valid */ 852 #define ETH_DMARXNDESCRF_BUF1V ( ( uint32_t ) 0x01000000U ) /*!< Buffer 1 Address Valid */ 853 854 /* 855 * DMA Rx Normal Descriptor write back format 856 * --------------------------------------------------------------------------------------------------------------------- 857 * RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] | 858 * --------------------------------------------------------------------------------------------------------------------- 859 * RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status | 860 * --------------------------------------------------------------------------------------------------------------------- 861 * RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] | 862 * --------------------------------------------------------------------------------------------------------------------- 863 * RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] | 864 * --------------------------------------------------------------------------------------------------------------------- 865 */ 866 867 /** 868 * @brief Bit definition of Rx normal descriptor register 0 write back format 869 */ 870 #define ETH_DMARXNDESCWBF_IVT ( ( uint32_t ) 0xFFFF0000U ) /*!< Inner VLAN Tag */ 871 #define ETH_DMARXNDESCWBF_OVT ( ( uint32_t ) 0x0000FFFFU ) /*!< Outer VLAN Tag */ 872 873 /** 874 * @brief Bit definition of Rx normal descriptor register 1 write back format 875 */ 876 #define ETH_DMARXNDESCWBF_OPC ( ( uint32_t ) 0xFFFF0000U ) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */ 877 #define ETH_DMARXNDESCWBF_TD ( ( uint32_t ) 0x00008000U ) /*!< Timestamp Dropped */ 878 #define ETH_DMARXNDESCWBF_TSA ( ( uint32_t ) 0x00004000U ) /*!< Timestamp Available */ 879 #define ETH_DMARXNDESCWBF_PV ( ( uint32_t ) 0x00002000U ) /*!< PTP Version */ 880 #define ETH_DMARXNDESCWBF_PFT ( ( uint32_t ) 0x00001000U ) /*!< PTP Packet Type */ 881 #define ETH_DMARXNDESCWBF_PMT_NO ( ( uint32_t ) 0x00000000U ) /*!< PTP Message Type: No PTP message received */ 882 #define ETH_DMARXNDESCWBF_PMT_SYNC ( ( uint32_t ) 0x00000100U ) /*!< PTP Message Type: SYNC (all clock types) */ 883 #define ETH_DMARXNDESCWBF_PMT_FUP ( ( uint32_t ) 0x00000200U ) /*!< PTP Message Type: Follow_Up (all clock types) */ 884 #define ETH_DMARXNDESCWBF_PMT_DREQ ( ( uint32_t ) 0x00000300U ) /*!< PTP Message Type: Delay_Req (all clock types) */ 885 #define ETH_DMARXNDESCWBF_PMT_DRESP ( ( uint32_t ) 0x00000400U ) /*!< PTP Message Type: Delay_Resp (all clock types) */ 886 #define ETH_DMARXNDESCWBF_PMT_PDREQ ( ( uint32_t ) 0x00000500U ) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */ 887 #define ETH_DMARXNDESCWBF_PMT_PDRESP ( ( uint32_t ) 0x00000600U ) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */ 888 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ( ( uint32_t ) 0x00000700U ) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */ 889 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ( ( uint32_t ) 0x00000800U ) /*!< PTP Message Type: Announce */ 890 #define ETH_DMARXNDESCWBF_PMT_MANAG ( ( uint32_t ) 0x00000900U ) /*!< PTP Message Type: Management */ 891 #define ETH_DMARXNDESCWBF_PMT_SIGN ( ( uint32_t ) 0x00000A00U ) /*!< PTP Message Type: Signaling */ 892 #define ETH_DMARXNDESCWBF_PMT_RESERVED ( ( uint32_t ) 0x00000F00U ) /*!< PTP Message Type: PTP packet with Reserved message type */ 893 #define ETH_DMARXNDESCWBF_IPCE ( ( uint32_t ) 0x00000080U ) /*!< IP Payload Error */ 894 #define ETH_DMARXNDESCWBF_IPCB ( ( uint32_t ) 0x00000040U ) /*!< IP Checksum Bypassed */ 895 #define ETH_DMARXNDESCWBF_IPV6 ( ( uint32_t ) 0x00000020U ) /*!< IPv6 header Present */ 896 #define ETH_DMARXNDESCWBF_IPV4 ( ( uint32_t ) 0x00000010U ) /*!< IPv4 header Present */ 897 #define ETH_DMARXNDESCWBF_IPHE ( ( uint32_t ) 0x00000008U ) /*!< IP Header Error */ 898 #define ETH_DMARXNDESCWBF_PT ( ( uint32_t ) 0x00000003U ) /*!< Payload Type mask */ 899 #define ETH_DMARXNDESCWBF_PT_UNKNOWN ( ( uint32_t ) 0x00000000U ) /*!< Payload Type: Unknown type or IP/AV payload not processed */ 900 #define ETH_DMARXNDESCWBF_PT_UDP ( ( uint32_t ) 0x00000001U ) /*!< Payload Type: UDP */ 901 #define ETH_DMARXNDESCWBF_PT_TCP ( ( uint32_t ) 0x00000002U ) /*!< Payload Type: TCP */ 902 #define ETH_DMARXNDESCWBF_PT_ICMP ( ( uint32_t ) 0x00000003U ) /*!< Payload Type: ICMP */ 903 904 /** 905 * @brief Bit definition of Rx normal descriptor register 2 write back format 906 */ 907 #define ETH_DMARXNDESCWBF_L3L4FM ( ( uint32_t ) 0x20000000U ) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */ 908 #define ETH_DMARXNDESCWBF_L4FM ( ( uint32_t ) 0x10000000U ) /*!< Layer 4 Filter Match */ 909 #define ETH_DMARXNDESCWBF_L3FM ( ( uint32_t ) 0x08000000U ) /*!< Layer 3 Filter Match */ 910 #define ETH_DMARXNDESCWBF_MADRM ( ( uint32_t ) 0x07F80000U ) /*!< MAC Address Match or Hash Value */ 911 #define ETH_DMARXNDESCWBF_HF ( ( uint32_t ) 0x00040000U ) /*!< Hash Filter Status */ 912 #define ETH_DMARXNDESCWBF_DAF ( ( uint32_t ) 0x00020000U ) /*!< Destination Address Filter Fail */ 913 #define ETH_DMARXNDESCWBF_SAF ( ( uint32_t ) 0x00010000U ) /*!< SA Address Filter Fail */ 914 #define ETH_DMARXNDESCWBF_VF ( ( uint32_t ) 0x00008000U ) /*!< VLAN Filter Status */ 915 #define ETH_DMARXNDESCWBF_ARPNR ( ( uint32_t ) 0x00000400U ) /*!< ARP Reply Not Generated */ 916 917 918 /** 919 * @brief Bit definition of Rx normal descriptor register 3 write back format 920 */ 921 #define ETH_DMARXNDESCWBF_OWN ( ( uint32_t ) 0x80000000U ) /*!< Own Bit */ 922 #define ETH_DMARXNDESCWBF_CTXT ( ( uint32_t ) 0x40000000U ) /*!< Receive Context Descriptor */ 923 #define ETH_DMARXNDESCWBF_FD ( ( uint32_t ) 0x20000000U ) /*!< First Descriptor */ 924 #define ETH_DMARXNDESCWBF_LD ( ( uint32_t ) 0x10000000U ) /*!< Last Descriptor */ 925 #define ETH_DMARXNDESCWBF_RS2V ( ( uint32_t ) 0x08000000U ) /*!< Receive Status RDES2 Valid */ 926 #define ETH_DMARXNDESCWBF_RS1V ( ( uint32_t ) 0x04000000U ) /*!< Receive Status RDES1 Valid */ 927 #define ETH_DMARXNDESCWBF_RS0V ( ( uint32_t ) 0x02000000U ) /*!< Receive Status RDES0 Valid */ 928 #define ETH_DMARXNDESCWBF_CE ( ( uint32_t ) 0x01000000U ) /*!< CRC Error */ 929 #define ETH_DMARXNDESCWBF_GP ( ( uint32_t ) 0x00800000U ) /*!< Giant Packet */ 930 #define ETH_DMARXNDESCWBF_RWT ( ( uint32_t ) 0x00400000U ) /*!< Receive Watchdog Timeout */ 931 #define ETH_DMARXNDESCWBF_OE ( ( uint32_t ) 0x00200000U ) /*!< Overflow Error */ 932 #define ETH_DMARXNDESCWBF_RE ( ( uint32_t ) 0x00100000U ) /*!< Receive Error */ 933 #define ETH_DMARXNDESCWBF_DE ( ( uint32_t ) 0x00080000U ) /*!< Dribble Bit Error */ 934 #define ETH_DMARXNDESCWBF_LT ( ( uint32_t ) 0x00070000U ) /*!< Length/Type Field */ 935 #define ETH_DMARXNDESCWBF_LT_LP ( ( uint32_t ) 0x00000000U ) /*!< The packet is a length packet */ 936 #define ETH_DMARXNDESCWBF_LT_TP ( ( uint32_t ) 0x00010000U ) /*!< The packet is a type packet */ 937 #define ETH_DMARXNDESCWBF_LT_ARP ( ( uint32_t ) 0x00030000U ) /*!< The packet is a ARP Request packet type */ 938 #define ETH_DMARXNDESCWBF_LT_VLAN ( ( uint32_t ) 0x00040000U ) /*!< The packet is a type packet with VLAN Tag */ 939 #define ETH_DMARXNDESCWBF_LT_DVLAN ( ( uint32_t ) 0x00050000U ) /*!< The packet is a type packet with Double VLAN Tag */ 940 #define ETH_DMARXNDESCWBF_LT_MAC ( ( uint32_t ) 0x00060000U ) /*!< The packet is a MAC Control packet type */ 941 #define ETH_DMARXNDESCWBF_LT_OAM ( ( uint32_t ) 0x00070000U ) /*!< The packet is a OAM packet type */ 942 #define ETH_DMARXNDESCWBF_ES ( ( uint32_t ) 0x00008000U ) /*!< Error Summary */ 943 #define ETH_DMARXNDESCWBF_PL ( ( uint32_t ) 0x00007FFFU ) /*!< Packet Length */ 944 945 /* 946 * DMA Rx context Descriptor 947 * --------------------------------------------------------------------------------------------------------------------- 948 * RDES0 | Timestamp Low[31:0] | 949 * --------------------------------------------------------------------------------------------------------------------- 950 * RDES1 | Timestamp High[31:0] | 951 * --------------------------------------------------------------------------------------------------------------------- 952 * RDES2 | Reserved | 953 * --------------------------------------------------------------------------------------------------------------------- 954 * RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] | 955 * --------------------------------------------------------------------------------------------------------------------- 956 */ 957 958 /** 959 * @brief Bit definition of Rx context descriptor register 0 960 */ 961 #define ETH_DMARXCDESC_RTSL ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Receive Packet Timestamp Low */ 962 963 /** 964 * @brief Bit definition of Rx context descriptor register 1 965 */ 966 #define ETH_DMARXCDESC_RTSH ( ( uint32_t ) 0xFFFFFFFFU ) /*!< Receive Packet Timestamp High */ 967 968 /** 969 * @brief Bit definition of Rx context descriptor register 3 970 */ 971 #define ETH_DMARXCDESC_OWN ( ( uint32_t ) 0x80000000U ) /*!< Own Bit */ 972 #define ETH_DMARXCDESC_CTXT ( ( uint32_t ) 0x40000000U ) /*!< Receive Context Descriptor */ 973 974 /** 975 * @} 976 */ 977 978 /** @defgroup ETH_Frame_settings ETH frame settings 979 * @{ 980 */ 981 #define ETH_MAX_PACKET_SIZE ( ( uint32_t ) 1528U ) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 982 #define ETH_HEADER ( ( uint32_t ) 14U ) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 983 #define ETH_CRC ( ( uint32_t ) 4U ) /*!< Ethernet CRC */ 984 #define ETH_VLAN_TAG ( ( uint32_t ) 4U ) /*!< optional 802.1q VLAN Tag */ 985 #define ETH_MIN_PAYLOAD ( ( uint32_t ) 46U ) /*!< Minimum Ethernet payload size */ 986 #define ETH_MAX_PAYLOAD ( ( uint32_t ) 1500U ) /*!< Maximum Ethernet payload size */ 987 #define ETH_JUMBO_FRAME_PAYLOAD ( ( uint32_t ) 9000U ) /*!< Jumbo frame payload size */ 988 989 /** 990 * @} 991 */ 992 993 /** @defgroup ETH_Error_Code ETH Error Code 994 * @{ 995 */ 996 #define HAL_ETH_ERROR_NONE ( ( uint32_t ) 0x00000000U ) /*!< No error */ 997 #define HAL_ETH_ERROR_PARAM ( ( uint32_t ) 0x00000001U ) /*!< Busy error */ 998 #define HAL_ETH_ERROR_BUSY ( ( uint32_t ) 0x00000002U ) /*!< Parameter error */ 999 #define HAL_ETH_ERROR_TIMEOUT ( ( uint32_t ) 0x00000004U ) /*!< Timeout error */ 1000 #define HAL_ETH_ERROR_DMA ( ( uint32_t ) 0x00000008U ) /*!< DMA transfer error */ 1001 #define HAL_ETH_ERROR_MAC ( ( uint32_t ) 0x00000010U ) /*!< MAC transfer error */ 1002 #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) 1003 #define HAL_ETH_ERROR_INVALID_CALLBACK ( ( uint32_t ) 0x00000020U ) /*!< Invalid Callback error */ 1004 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 1005 1006 /** 1007 * @} 1008 */ 1009 1010 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes 1011 * @{ 1012 */ 1013 #define ETH_TX_PACKETS_FEATURES_CSUM ( ( uint32_t ) 0x00000001U ) 1014 #define ETH_TX_PACKETS_FEATURES_SAIC ( ( uint32_t ) 0x00000002U ) 1015 #define ETH_TX_PACKETS_FEATURES_VLANTAG ( ( uint32_t ) 0x00000004U ) 1016 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ( ( uint32_t ) 0x00000008U ) 1017 #define ETH_TX_PACKETS_FEATURES_TSO ( ( uint32_t ) 0x00000010U ) 1018 #define ETH_TX_PACKETS_FEATURES_CRCPAD ( ( uint32_t ) 0x00000020U ) 1019 1020 /** 1021 * @} 1022 */ 1023 1024 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control 1025 * @{ 1026 */ 1027 #define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE 1028 #define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT 1029 #define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE 1030 1031 /** 1032 * @} 1033 */ 1034 1035 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control 1036 * @{ 1037 */ 1038 #define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE 1039 #define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT 1040 #define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT 1041 #define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE 1042 1043 /** 1044 * @} 1045 */ 1046 1047 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control 1048 * @{ 1049 */ 1050 #define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE 1051 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 1052 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 1053 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 1054 1055 /** 1056 * @} 1057 */ 1058 1059 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control 1060 * @{ 1061 */ 1062 #define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE 1063 #define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE 1064 #define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT 1065 #define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE 1066 1067 /** 1068 * @} 1069 */ 1070 1071 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control 1072 * @{ 1073 */ 1074 #define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE 1075 #define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE 1076 #define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT 1077 #define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE 1078 1079 /** 1080 * @} 1081 */ 1082 1083 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status 1084 * @{ 1085 */ 1086 #define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB 1087 #define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE 1088 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE 1089 1090 /** 1091 * @} 1092 */ 1093 1094 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type 1095 * @{ 1096 */ 1097 #define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4 1098 #define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6 1099 1100 /** 1101 * @} 1102 */ 1103 1104 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type 1105 * @{ 1106 */ 1107 #define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN 1108 #define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP 1109 #define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP 1110 #define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP 1111 1112 /** 1113 * @} 1114 */ 1115 1116 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status 1117 * @{ 1118 */ 1119 #define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF 1120 #define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF 1121 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF 1122 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF 1123 1124 /** 1125 * @} 1126 */ 1127 1128 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status 1129 * @{ 1130 */ 1131 #define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM 1132 #define ETH_L3_FILTER1_MATCH ( ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM ) 1133 1134 /** 1135 * @} 1136 */ 1137 1138 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status 1139 * @{ 1140 */ 1141 #define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM 1142 #define ETH_L4_FILTER1_MATCH ( ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM ) 1143 1144 /** 1145 * @} 1146 */ 1147 1148 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code 1149 * @{ 1150 */ 1151 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE 1152 #define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE 1153 #define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE 1154 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT 1155 #define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP 1156 #define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE 1157 1158 /** 1159 * @} 1160 */ 1161 1162 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1163 * @{ 1164 */ 1165 #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA 1166 #define ETH_DMAARBITRATION_RX1_TX1 ( ( uint32_t ) 0x00000000U ) 1167 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1 1168 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1 1169 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1 1170 #define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1 1171 #define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1 1172 #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1 1173 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1 1174 #define ETH_DMAARBITRATION_TX ( ETH_DMAMR_TXPR | ETH_DMAMR_DA ) 1175 #define ETH_DMAARBITRATION_TX1_RX1 ( ( uint32_t ) 0x00000000U ) 1176 #define ETH_DMAARBITRATION_TX2_RX1 ( ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1 ) 1177 #define ETH_DMAARBITRATION_TX3_RX1 ( ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1 ) 1178 #define ETH_DMAARBITRATION_TX4_RX1 ( ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1 ) 1179 #define ETH_DMAARBITRATION_TX5_RX1 ( ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1 ) 1180 #define ETH_DMAARBITRATION_TX6_RX1 ( ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1 ) 1181 #define ETH_DMAARBITRATION_TX7_RX1 ( ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1 ) 1182 #define ETH_DMAARBITRATION_TX8_RX1 ( ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1 ) 1183 1184 /** 1185 * @} 1186 */ 1187 1188 /** @defgroup ETH_Burst_Mode ETH Burst Mode 1189 * @{ 1190 */ 1191 #define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB 1192 #define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB 1193 #define ETH_BURSTLENGTH_UNSPECIFIED ( ( uint32_t ) 0x00000000U ) 1194 1195 /** 1196 * @} 1197 */ 1198 1199 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1200 * @{ 1201 */ 1202 #define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL 1203 #define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL 1204 #define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL 1205 #define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL 1206 #define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL 1207 #define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL 1208 1209 /** 1210 * @} 1211 */ 1212 1213 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1214 * @{ 1215 */ 1216 #define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL 1217 #define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL 1218 #define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL 1219 #define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL 1220 #define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL 1221 #define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL 1222 1223 /** 1224 * @} 1225 */ 1226 1227 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1228 * @{ 1229 */ 1230 #define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE 1231 #define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE 1232 #define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE 1233 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE 1234 #define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE 1235 #define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE 1236 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE 1237 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE 1238 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE 1239 #define ETH_DMA_RX_IT ETH_DMACIER_RIE 1240 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE 1241 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE 1242 #define ETH_DMA_TX_IT ETH_DMACIER_TIE 1243 1244 /** 1245 * @} 1246 */ 1247 1248 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags 1249 * @{ 1250 */ 1251 #define ETH_DMA_RX_NO_ERROR_FLAG ( ( uint32_t ) 0x00000000U ) 1252 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG ( ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0 ) 1253 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG ( ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 ) 1254 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG ( ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0 ) 1255 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2 1256 #define ETH_DMA_TX_NO_ERROR_FLAG ( ( uint32_t ) 0x00000000U ) 1257 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG ( ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0 ) 1258 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG ( ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 ) 1259 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG ( ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0 ) 1260 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2 1261 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE 1262 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE 1263 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI 1264 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT 1265 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS 1266 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU 1267 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS 1268 1269 /** 1270 * @} 1271 */ 1272 1273 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode 1274 * @{ 1275 */ 1276 #define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF 1277 #define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS 1278 #define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS 1279 #define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS 1280 #define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS 1281 #define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS 1282 #define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS 1283 #define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS 1284 #define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS 1285 1286 /** 1287 * @} 1288 */ 1289 1290 /** @defgroup ETH_Receive_Mode ETH Receive Mode 1291 * @{ 1292 */ 1293 #define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF 1294 #define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS 1295 #define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS 1296 #define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS 1297 #define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS 1298 1299 /** 1300 * @} 1301 */ 1302 1303 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1304 * @{ 1305 */ 1306 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4 1307 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28 1308 #define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36 1309 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144 1310 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256 1311 #define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512 1312 1313 /** 1314 * @} 1315 */ 1316 1317 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout 1318 * @{ 1319 */ 1320 #define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB 1321 #define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB 1322 #define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB 1323 #define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB 1324 #define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB 1325 #define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB 1326 #define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB 1327 #define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB 1328 #define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB 1329 #define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB 1330 #define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB 1331 #define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB 1332 #define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB 1333 #define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB 1334 #define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB 1335 1336 /** 1337 * @} 1338 */ 1339 1340 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap 1341 * @{ 1342 */ 1343 #define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT 1344 #define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT 1345 #define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT 1346 #define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT 1347 #define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT 1348 #define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT 1349 #define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT 1350 #define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT 1351 1352 /** 1353 * @} 1354 */ 1355 1356 /** @defgroup ETH_Speed ETH Speed 1357 * @{ 1358 */ 1359 #define ETH_SPEED_10M ( ( uint32_t ) 0x00000000U ) 1360 #define ETH_SPEED_100M ETH_MACCR_FES 1361 1362 /** 1363 * @} 1364 */ 1365 1366 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 1367 * @{ 1368 */ 1369 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM 1370 #define ETH_HALFDUPLEX_MODE ( ( uint32_t ) 0x00000000U ) 1371 1372 /** 1373 * @} 1374 */ 1375 1376 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1377 * @{ 1378 */ 1379 #define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10 1380 #define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8 1381 #define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4 1382 #define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1 1383 1384 /** 1385 * @} 1386 */ 1387 1388 /** @defgroup ETH_Preamble_Length ETH Preamble Length 1389 * @{ 1390 */ 1391 #define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7 1392 #define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5 1393 #define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3 1394 1395 /** 1396 * @} 1397 */ 1398 1399 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control 1400 * @{ 1401 */ 1402 #define ETH_SOURCEADDRESS_DISABLE ( ( uint32_t ) 0x00000000U ) 1403 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 1404 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 1405 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 1406 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1 1407 1408 /** 1409 * @} 1410 */ 1411 1412 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter 1413 * @{ 1414 */ 1415 #define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL 1416 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA 1417 #define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL 1418 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER 1419 1420 /** 1421 * @} 1422 */ 1423 1424 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1425 * @{ 1426 */ 1427 #define ETH_VLANTAGCOMPARISON_16BIT ( ( uint32_t ) 0x00000000U ) 1428 #define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV 1429 1430 /** 1431 * @} 1432 */ 1433 1434 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1435 * @{ 1436 */ 1437 #define ETH_MAC_ADDRESS0 ( ( uint32_t ) 0x00000000U ) 1438 #define ETH_MAC_ADDRESS1 ( ( uint32_t ) 0x00000008U ) 1439 #define ETH_MAC_ADDRESS2 ( ( uint32_t ) 0x00000010U ) 1440 #define ETH_MAC_ADDRESS3 ( ( uint32_t ) 0x00000018U ) 1441 1442 /** 1443 * @} 1444 */ 1445 1446 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1447 * @{ 1448 */ 1449 #define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE 1450 #define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE 1451 #define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE 1452 #define ETH_MAC_LPI_IT ETH_MACIER_LPIIE 1453 #define ETH_MAC_PMT_IT ETH_MACIER_PMTIE 1454 #define ETH_MAC_PHY_IT ETH_MACIER_PHYIE 1455 1456 /** 1457 * @} 1458 */ 1459 1460 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event 1461 * @{ 1462 */ 1463 #define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD 1464 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD 1465 1466 /** 1467 * @} 1468 */ 1469 1470 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status 1471 * @{ 1472 */ 1473 #define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT 1474 #define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL 1475 #define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL 1476 #define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF 1477 #define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR 1478 #define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR 1479 #define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT 1480 1481 /** 1482 * @} 1483 */ 1484 1485 /** @defgroup HAL_ETH_StateTypeDef ETH States 1486 * @{ 1487 */ 1488 #define HAL_ETH_STATE_RESET ( ( uint32_t ) 0x00000000U ) /*!< Peripheral not yet Initialized or disabled */ 1489 #define HAL_ETH_STATE_READY ( ( uint32_t ) 0x00000010U ) /*!< Peripheral Communication started */ 1490 #define HAL_ETH_STATE_BUSY ( ( uint32_t ) 0x00000023U ) /*!< an internal process is ongoing */ 1491 #define HAL_ETH_STATE_BUSY_TX ( ( uint32_t ) 0x00000021U ) /*!< Transmission process is ongoing */ 1492 #define HAL_ETH_STATE_BUSY_RX ( ( uint32_t ) 0x00000022U ) /*!< Reception process is ongoing */ 1493 #define HAL_ETH_STATE_ERROR ( ( uint32_t ) 0x000000E0U ) /*!< Error State */ 1494 1495 /** 1496 * @} 1497 */ 1498 1499 /** 1500 * @} 1501 */ 1502 1503 /* Exported macro ------------------------------------------------------------*/ 1504 1505 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1506 * @{ 1507 */ 1508 1509 /** @brief Reset ETH handle state 1510 * @param __HANDLE__: specifies the ETH handle. 1511 * @retval None 1512 */ 1513 #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) 1514 #define __HAL_ETH_RESET_HANDLE_STATE( __HANDLE__ ) \ 1515 do { \ 1516 ( __HANDLE__ )->gState = HAL_ETH_STATE_RESET; \ 1517 ( __HANDLE__ )->RxState = HAL_ETH_STATE_RESET; \ 1518 ( __HANDLE__ )->MspInitCallback = NULL; \ 1519 ( __HANDLE__ )->MspDeInitCallback = NULL; \ 1520 } while( 0 ) 1521 #else 1522 #define __HAL_ETH_RESET_HANDLE_STATE( __HANDLE__ ) \ 1523 do { \ 1524 ( __HANDLE__ )->gState = HAL_ETH_STATE_RESET; \ 1525 ( __HANDLE__ )->RxState = HAL_ETH_STATE_RESET; \ 1526 } while( 0 ) 1527 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1528 1529 /** 1530 * @brief Enables the specified ETHERNET DMA interrupts. 1531 * @param __HANDLE__ : ETH Handle 1532 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1533 * enabled @ref ETH_DMA_Interrupts 1534 * @retval None 1535 */ 1536 #define __HAL_ETH_DMA_ENABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMACIER |= ( __INTERRUPT__ ) ) 1537 1538 /** 1539 * @brief Disables the specified ETHERNET DMA interrupts. 1540 * @param __HANDLE__ : ETH Handle 1541 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1542 * disabled. @ref ETH_DMA_Interrupts 1543 * @retval None 1544 */ 1545 #define __HAL_ETH_DMA_DISABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMACIER &= ~( __INTERRUPT__ ) ) 1546 1547 /** 1548 * @brief Gets the ETHERNET DMA IT source enabled or disabled. 1549 * @param __HANDLE__ : ETH Handle 1550 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1551 * @retval The ETH DMA IT Source enabled or disabled 1552 */ 1553 #define __HAL_ETH_DMA_GET_IT_SOURCE( __HANDLE__, __INTERRUPT__ ) ( ( ( __HANDLE__ )->Instance->DMACIER & ( __INTERRUPT__ ) ) == ( __INTERRUPT__ ) ) 1554 1555 /** 1556 * @brief Gets the ETHERNET DMA IT pending bit. 1557 * @param __HANDLE__ : ETH Handle 1558 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1559 * @retval The state of ETH DMA IT (SET or RESET) 1560 */ 1561 #define __HAL_ETH_DMA_GET_IT( __HANDLE__, __INTERRUPT__ ) ( ( ( __HANDLE__ )->Instance->DMACSR & ( __INTERRUPT__ ) ) == ( __INTERRUPT__ ) ) 1562 1563 /** 1564 * @brief Clears the ETHERNET DMA IT pending bit. 1565 * @param __HANDLE__ : ETH Handle 1566 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1567 * @retval None 1568 */ 1569 #define __HAL_ETH_DMA_CLEAR_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->DMACSR = ( __INTERRUPT__ ) ) 1570 1571 /** 1572 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1573 * @param __HANDLE__: ETH Handle 1574 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1575 * @retval The state of ETH DMA FLAG (SET or RESET). 1576 */ 1577 #define __HAL_ETH_DMA_GET_FLAG( __HANDLE__, __FLAG__ ) ( ( ( __HANDLE__ )->Instance->DMACSR & ( __FLAG__ ) ) == ( __FLAG__ ) ) 1578 1579 /** 1580 * @brief Clears the specified ETHERNET DMA flag. 1581 * @param __HANDLE__: ETH Handle 1582 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1583 * @retval The state of ETH DMA FLAG (SET or RESET). 1584 */ 1585 #define __HAL_ETH_DMA_CLEAR_FLAG( __HANDLE__, __FLAG__ ) ( ( __HANDLE__ )->Instance->DMACSR = ( __FLAG__ ) ) 1586 1587 /** 1588 * @brief Enables the specified ETHERNET MAC interrupts. 1589 * @param __HANDLE__ : ETH Handle 1590 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1591 * enabled @ref ETH_MAC_Interrupts 1592 * @retval None 1593 */ 1594 #define __HAL_ETH_MAC_ENABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MACIER |= ( __INTERRUPT__ ) ) 1595 1596 /** 1597 * @brief Disables the specified ETHERNET MAC interrupts. 1598 * @param __HANDLE__ : ETH Handle 1599 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1600 * enabled @ref ETH_MAC_Interrupts 1601 * @retval None 1602 */ 1603 #define __HAL_ETH_MAC_DISABLE_IT( __HANDLE__, __INTERRUPT__ ) ( ( __HANDLE__ )->Instance->MACIER &= ~( __INTERRUPT__ ) ) 1604 1605 /** 1606 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1607 * @param __HANDLE__: ETH Handle 1608 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts 1609 * @retval The state of ETH MAC IT (SET or RESET). 1610 */ 1611 #define __HAL_ETH_MAC_GET_IT( __HANDLE__, __INTERRUPT__ ) ( ( ( __HANDLE__ )->Instance->MACISR & ( __INTERRUPT__ ) ) == ( __INTERRUPT__ ) ) 1612 1613 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ 1614 #define ETH_WAKEUP_EXTI_LINE ( ( uint32_t ) 0x00400000U ) /* !< 86 - 64 = 22 */ 1615 1616 /** 1617 * @brief Enable the ETH WAKEUP Exti Line. 1618 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1619 * @arg ETH_WAKEUP_EXTI_LINE 1620 * @retval None. 1621 */ 1622 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT( __EXTI_LINE__ ) ( EXTI_D1->IMR3 |= ( __EXTI_LINE__ ) ) 1623 1624 /** 1625 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1626 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1627 * @arg ETH_WAKEUP_EXTI_LINE 1628 * @retval EXTI ETH WAKEUP Line Status. 1629 */ 1630 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG( __EXTI_LINE__ ) ( EXTI_D1->PR3 & ( __EXTI_LINE__ ) ) 1631 1632 /** 1633 * @brief Clear the ETH WAKEUP Exti flag. 1634 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1635 * @arg ETH_WAKEUP_EXTI_LINE 1636 * @retval None. 1637 */ 1638 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG( __EXTI_LINE__ ) ( EXTI_D1->PR3 = ( __EXTI_LINE__ ) ) 1639 1640 #if defined( DUAL_CORE ) 1641 1642 /** 1643 * @brief Enable the ETH WAKEUP Exti Line by Core2. 1644 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1645 * @arg ETH_WAKEUP_EXTI_LINE 1646 * @retval None. 1647 */ 1648 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT( __EXTI_LINE__ ) ( EXTI_D2->IMR3 |= ( __EXTI_LINE__ ) ) 1649 1650 /** 1651 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1652 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1653 * @arg ETH_WAKEUP_EXTI_LINE 1654 * @retval EXTI ETH WAKEUP Line Status. 1655 */ 1656 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG( __EXTI_LINE__ ) ( EXTI_D2->PR3 & ( __EXTI_LINE__ ) ) 1657 1658 /** 1659 * @brief Clear the ETH WAKEUP Exti flag. 1660 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1661 * @arg ETH_WAKEUP_EXTI_LINE 1662 * @retval None. 1663 */ 1664 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG( __EXTI_LINE__ ) ( EXTI_D2->PR3 = ( __EXTI_LINE__ ) ) 1665 #endif 1666 1667 /** 1668 * @brief enable rising edge interrupt on selected EXTI line. 1669 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1670 * @arg ETH_WAKEUP_EXTI_LINE 1671 * @retval None 1672 */ 1673 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE( __EXTI_LINE__ ) \ 1674 ( EXTI->FTSR3 &= ~( __EXTI_LINE__ ) ); \ 1675 ( EXTI->RTSR3 |= ( __EXTI_LINE__ ) ) 1676 1677 /** 1678 * @brief enable falling edge interrupt on selected EXTI line. 1679 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1680 * @arg ETH_WAKEUP_EXTI_LINE 1681 * @retval None 1682 */ 1683 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE( __EXTI_LINE__ ) \ 1684 ( EXTI->RTSR3 &= ~( __EXTI_LINE__ ) ); \ 1685 ( EXTI->FTSR3 |= ( __EXTI_LINE__ ) ) 1686 1687 /** 1688 * @brief enable falling edge interrupt on selected EXTI line. 1689 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1690 * @arg ETH_WAKEUP_EXTI_LINE 1691 * @retval None 1692 */ 1693 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE( __EXTI_LINE__ ) \ 1694 ( EXTI->RTSR3 |= ( __EXTI_LINE__ ) ); \ 1695 ( EXTI->FTSR3 |= ( __EXTI_LINE__ ) ) 1696 1697 /** 1698 * @brief Generates a Software interrupt on selected EXTI line. 1699 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1700 * @arg ETH_WAKEUP_EXTI_LINE 1701 * @retval None 1702 */ 1703 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT( __EXTI_LINE__ ) ( EXTI->SWIER3 |= ( __EXTI_LINE__ ) ) 1704 1705 /** 1706 * @} 1707 */ 1708 1709 /* Include ETH HAL Extension module */ 1710 #include "stm32h7xx_hal_eth_ex.h" 1711 1712 /* Exported functions --------------------------------------------------------*/ 1713 1714 /** @addtogroup ETH_Exported_Functions 1715 * @{ 1716 */ 1717 1718 /** @addtogroup ETH_Exported_Functions_Group1 1719 * @{ 1720 */ 1721 /* Initialization and de initialization functions **********************************/ 1722 HAL_StatusTypeDef HAL_ETH_Init( ETH_HandleTypeDef * heth ); 1723 HAL_StatusTypeDef HAL_ETH_DeInit( ETH_HandleTypeDef * heth ); 1724 void HAL_ETH_MspInit( ETH_HandleTypeDef * heth ); 1725 void HAL_ETH_MspDeInit( ETH_HandleTypeDef * heth ); 1726 HAL_StatusTypeDef HAL_ETH_DescAssignMemory( ETH_HandleTypeDef * heth, 1727 uint32_t Index, 1728 uint8_t * pBuffer1, 1729 uint8_t * pBuffer2 ); 1730 1731 /* Callbacks Register/UnRegister functions ***********************************/ 1732 #if ( USE_HAL_ETH_REGISTER_CALLBACKS == 1 ) 1733 HAL_StatusTypeDef HAL_ETH_RegisterCallback( ETH_HandleTypeDef * heth, 1734 HAL_ETH_CallbackIDTypeDef CallbackID, 1735 pETH_CallbackTypeDef pCallback ); 1736 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback( ETH_HandleTypeDef * heth, 1737 HAL_ETH_CallbackIDTypeDef CallbackID ); 1738 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 1739 1740 /** 1741 * @} 1742 */ 1743 1744 /** @addtogroup ETH_Exported_Functions_Group2 1745 * @{ 1746 */ 1747 /* IO operation functions *******************************************************/ 1748 HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef * heth ); 1749 HAL_StatusTypeDef HAL_ETH_Start_IT( ETH_HandleTypeDef * heth ); 1750 HAL_StatusTypeDef HAL_ETH_Stop( ETH_HandleTypeDef * heth ); 1751 HAL_StatusTypeDef HAL_ETH_Stop_IT( ETH_HandleTypeDef * heth ); 1752 1753 uint8_t HAL_ETH_IsRxDataAvailable( ETH_HandleTypeDef * heth ); 1754 /* The following 2 functions are replaced with a single function: HAL_ETH_GetRxData(). */ 1755 /* HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer); */ 1756 /* HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length); */ 1757 1758 size_t HAL_ETH_GetRxData( ETH_HandleTypeDef * heth, 1759 ETH_BufferTypeDef * RxBuffer ); 1760 1761 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo( ETH_HandleTypeDef * heth, 1762 ETH_RxPacketInfo * RxPacketInfo ); 1763 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors( ETH_HandleTypeDef * heth, 1764 uint8_t * pucNewBuffer ); 1765 1766 HAL_StatusTypeDef HAL_ETH_Transmit( ETH_HandleTypeDef * heth, 1767 ETH_TxPacketConfig * pTxConfig, 1768 uint32_t Timeout ); 1769 HAL_StatusTypeDef HAL_ETH_Transmit_IT( ETH_HandleTypeDef * heth, 1770 ETH_TxPacketConfig * pTxConfig ); 1771 1772 void ETH_Clear_Tx_Descriptors( ETH_HandleTypeDef * heth ); 1773 1774 1775 HAL_StatusTypeDef HAL_ETH_WritePHYRegister( ETH_HandleTypeDef * heth, 1776 uint32_t PHYAddr, 1777 uint32_t PHYReg, 1778 uint32_t RegValue ); 1779 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister( ETH_HandleTypeDef * heth, 1780 uint32_t PHYAddr, 1781 uint32_t PHYReg, 1782 uint32_t * pRegValue ); 1783 1784 void HAL_ETH_IRQHandler( ETH_HandleTypeDef * heth ); 1785 void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef * heth ); 1786 void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef * heth ); 1787 void HAL_ETH_DMAErrorCallback( ETH_HandleTypeDef * heth ); 1788 void HAL_ETH_MACErrorCallback( ETH_HandleTypeDef * heth ); 1789 void HAL_ETH_PMTCallback( ETH_HandleTypeDef * heth ); 1790 void HAL_ETH_EEECallback( ETH_HandleTypeDef * heth ); 1791 void HAL_ETH_WakeUpCallback( ETH_HandleTypeDef * heth ); 1792 1793 /** 1794 * @} 1795 */ 1796 1797 /** @addtogroup ETH_Exported_Functions_Group3 1798 * @{ 1799 */ 1800 /* Peripheral Control functions **********************************************/ 1801 /* MAC & DMA Configuration APIs **********************************************/ 1802 HAL_StatusTypeDef HAL_ETH_GetMACConfig( ETH_HandleTypeDef * heth, 1803 ETH_MACConfigTypeDef * macconf ); 1804 HAL_StatusTypeDef HAL_ETH_GetDMAConfig( ETH_HandleTypeDef * heth, 1805 ETH_DMAConfigTypeDef * dmaconf ); 1806 HAL_StatusTypeDef HAL_ETH_SetMACConfig( ETH_HandleTypeDef * heth, 1807 ETH_MACConfigTypeDef * macconf ); 1808 HAL_StatusTypeDef HAL_ETH_SetDMAConfig( ETH_HandleTypeDef * heth, 1809 ETH_DMAConfigTypeDef * dmaconf ); 1810 1811 /* MAC VLAN Processing APIs ************************************************/ 1812 void HAL_ETH_SetRxVLANIdentifier( ETH_HandleTypeDef * heth, 1813 uint32_t ComparisonBits, 1814 uint32_t VLANIdentifier ); 1815 1816 /* MAC L2 Packet Filtering APIs **********************************************/ 1817 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig( ETH_HandleTypeDef * heth, 1818 ETH_MACFilterConfigTypeDef * pFilterConfig ); 1819 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig( ETH_HandleTypeDef * heth, 1820 ETH_MACFilterConfigTypeDef * pFilterConfig ); 1821 HAL_StatusTypeDef HAL_ETH_SetHashTable( ETH_HandleTypeDef * heth, 1822 uint32_t * pHashTable ); 1823 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch( ETH_HandleTypeDef * heth, 1824 uint32_t AddrNbr, 1825 uint8_t * pMACAddr ); 1826 1827 /* MAC Power Down APIs *****************************************************/ 1828 void HAL_ETH_EnterPowerDownMode( ETH_HandleTypeDef * heth, 1829 ETH_PowerDownConfigTypeDef * pPowerDownConfig ); 1830 void HAL_ETH_ExitPowerDownMode( ETH_HandleTypeDef * heth ); 1831 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter( ETH_HandleTypeDef * heth, 1832 uint32_t * pFilter, 1833 uint32_t Count ); 1834 1835 /** 1836 * @} 1837 */ 1838 1839 /** @addtogroup ETH_Exported_Functions_Group4 1840 * @{ 1841 */ 1842 /* Peripheral State functions **************************************************/ 1843 HAL_ETH_StateTypeDef HAL_ETH_GetState( ETH_HandleTypeDef * heth ); 1844 uint32_t HAL_ETH_GetError( ETH_HandleTypeDef * heth ); 1845 uint32_t HAL_ETH_GetDMAError( ETH_HandleTypeDef * heth ); 1846 uint32_t HAL_ETH_GetMACError( ETH_HandleTypeDef * heth ); 1847 uint32_t HAL_ETH_GetMACWakeUpSource( ETH_HandleTypeDef * heth ); 1848 1849 /** 1850 * @} 1851 */ 1852 1853 /** 1854 * @} 1855 */ 1856 1857 /** 1858 * @} 1859 */ 1860 1861 /** 1862 * @} 1863 */ 1864 1865 #endif /* ETH */ 1866 1867 #ifdef __cplusplus 1868 } 1869 #endif 1870 1871 #endif /* STM32Hxx_HAL_ETH_H */ 1872 1873 1874 1875 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1876
xref:
/FreeRTOS-Plus-TCP-v4.0.0/source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.h
(revision 14b3e241f530bb5beae65cefb3ce93cfa301b803)