xref: /FreeRTOS-Plus-TCP-v4.0.0/source/portable/NetworkInterface/ATSAM4E/ethernet_phy.h (revision 245d5879903cfc6e52a466fc1067fe54f869740c) 
1 /**
2  * \file
3  *
4  * \brief KSZ8051MNL (Ethernet PHY) driver for SAM.
5  *
6  * Copyright (c) 2013 Atmel Corporation. All rights reserved.
7  *
8  * \asf_license_start
9  *
10  * \page License
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions are met:
14  *
15  * 1. Redistributions of source code must retain the above copyright notice,
16  *    this list of conditions and the following disclaimer.
17  *
18  * 2. Redistributions in binary form must reproduce the above copyright notice,
19  *    this list of conditions and the following disclaimer in the documentation
20  *    and/or other materials provided with the distribution.
21  *
22  * 3. The name of Atmel may not be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  * 4. This software may only be redistributed and used in connection with an
26  *    Atmel microcontroller product.
27  *
28  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  *
40  * \asf_license_stop
41  *
42  */
43 
44 #ifndef ETHERNET_PHY_H_INCLUDED
45     #define ETHERNET_PHY_H_INCLUDED
46 
47     #include "compiler.h"
48 
49     #ifdef __cplusplus
50         extern "C" {
51     #endif
52 
53 /* IEEE defined Registers */
54     #define GMII_BMCR        0x00 /* Basic Control */
55     #define GMII_BMSR        0x01 /* Basic Status */
56     #define GMII_PHYID1      0x02 /* PHY Identifier 1 */
57     #define GMII_PHYID2      0x03 /* PHY Identifier 2 */
58     #define GMII_ANAR        0x04 /* Auto_Negotiation Advertisement */
59     #define GMII_ANLPAR      0x05 /* Auto_negotiation Link Partner Ability */
60     #define GMII_ANER        0x06 /* Auto-negotiation Expansion */
61     #define GMII_ANNPR       0x07 /* Auto-negotiation Next Page */
62     #define GMII_ANLPNPAR    0x08 /* Link Partner Next Page Ability */
63 /*#define GMII_1000BTCR    9   // 1000Base-T Control  // Reserved */
64 /*#define GMII_1000BTSR   10   // 1000Base-T Status   // Reserved */
65     #define GMII_AFECR1      0x11 /* AFE Control 1 */
66 /*#define GMII_ERDWR      12   // Extend Register - Data Write Register */
67 /*#define GMII_ERDRR      13   // Extend Register - Data Read Register */
68 /*14    reserved */
69     #define GMII_RXERCR             0x15 /* RXER Counter */
70 
71     #define PHY_REG_01_BMSR         0x01 /* Basic mode status register */
72     #define PHY_REG_02_PHYSID1      0x02 /* PHYS ID 1 */
73     #define PHY_REG_03_PHYSID2      0x03 /* PHYS ID 2 */
74     #define PHY_REG_04_ADVERTISE    0x04 /* Advertisement control reg */
75     #define PHY_REG_05_LPA          0x05 /* Link partner ability reg */
76     #define PHY_REG_06_ANER         0x06 /*	6	RW		Auto-Negotiation Expansion Register */
77     #define PHY_REG_07_ANNPTR       0x07 /*	7	RW		Auto-Negotiation Next Page TX */
78     #define PHY_REG_08_RESERVED0    0x08 /* 0x08..0x0Fh	8-15	RW		RESERVED */
79 
80     #define PHY_REG_10_PHYSTS       0x10 /* 16	RO		PHY Status Register */
81     #define PHY_REG_11_MICR         0x11 /* 17	RW		MII Interrupt Control Register */
82     #define PHY_REG_12_MISR         0x12 /* 18	RO		MII Interrupt Status Register */
83     #define PHY_REG_13_RESERVED1    0x13 /* 19	RW		RESERVED */
84     #define PHY_REG_14_FCSCR        0x14 /* 20	RO		False Carrier Sense Counter Register */
85     #define PHY_REG_15_RECR         0x15 /* 21	RO		Receive Error Counter Register */
86     #define PHY_REG_16_PCSR         0x16 /* 22	RW		PCS Sub-Layer Configuration and Status Register */
87     #define PHY_REG_17_RBR          0x17 /* 23	RW		RMII and Bypass Register */
88     #define PHY_REG_18_LEDCR        0x18 /* 24	RW		LED Direct Control Register */
89     #define PHY_REG_19_PHYCR        0x19 /* 25	RW		PHY Control Register */
90     #define PHY_REG_1A_10BTSCR      0x1A /* 26	RW		10Base-T Status/Control Register */
91     #define PHY_REG_1B_CDCTRL1      0x1B /* 27	RW		CD Test Control Register and BIST Extensions Register */
92     #define PHY_REG_1B_INT_CTRL     0x1B /* 27	RW		KSZ8041NL interrupt control */
93     #define PHY_REG_1C_RESERVED2    0x1C /* 28	RW		RESERVED */
94     #define PHY_REG_1D_EDCR         0x1D /* 29	RW		Energy Detect Control Register */
95     #define PHY_REG_1E_RESERVED3    0x1E /* */
96     #define PHY_REG_1F_RESERVED4    0x1F /* 30-31	RW		RESERVED */
97 
98     #define PHY_REG_1E_PHYCR_1      0x1E /* */
99     #define PHY_REG_1F_PHYCR_2      0x1F /* */
100 
101     #define PHY_SPEED_10            1
102     #define PHY_SPEED_100           2
103     #define PHY_SPEED_AUTO          ( PHY_SPEED_10 | PHY_SPEED_100 )
104 
105     #define PHY_MDIX_DIRECT         1
106     #define PHY_MDIX_CROSSED        2
107     #define PHY_MDIX_AUTO           ( PHY_MDIX_CROSSED | PHY_MDIX_DIRECT )
108 
109     #define PHY_DUPLEX_HALF         1
110     #define PHY_DUPLEX_FULL         2
111     #define PHY_DUPLEX_AUTO         ( PHY_DUPLEX_FULL | PHY_DUPLEX_HALF )
112 
113     typedef struct _SPhyProps
114     {
115         unsigned char speed;
116         unsigned char mdix;
117         unsigned char duplex;
118         unsigned char spare;
119     } SPhyProps;
120 
121     const char * phyPrintable( const SPhyProps * apProps );
122 
123     extern SPhyProps phyProps;
124 
125     #define GMII_OMSOR    0x16 /* Operation Mode Strap Override */
126     #define GMII_OMSSR    0x17 /* Operation Mode Strap Status */
127     #define GMII_ECR      0x18 /* Expanded Control */
128 /*#define GMII_DPPSR      19   // Digital PMA/PCS Status */
129 /*20    reserved */
130 /*#define GMII_RXERCR     21   // RXER Counter Register */
131 /*22-26 reserved */
132     #define GMII_ICSR    0x1B   /* Interrupt Control/Status */
133 /*#define GMII_DDC1R       28   // Digital Debug Control 1 Register */
134     #define GMII_LCSR    0x1D   /* LinkMD Control/Status */
135 
136 /*29-30 reserved */
137     #define GMII_PCR1    0x1E  /* PHY Control 1 */
138     #define GMII_PCR2    0x1F  /* PHY Control 2 */
139 
140 /*
141  * //Extend Registers
142  #define GMII_CCR        256  // Common Control Register
143  #define GMII_SSR        257  // Strap Status Register
144  #define GMII_OMSOR      258  // Operation Mode Strap Override Register
145  #define GMII_OMSSR      259  // Operation Mode Strap Status Register
146  #define GMII_RCCPSR     260  // RGMII Clock and Control Pad Skew Register
147  #define GMII_RRDPSR     261  // RGMII RX Data Pad Skew Register
148  #define GMII_ATR        263  // Analog Test Register
149  */
150 
151 
152 /* Bit definitions: GMII_BMCR 0x00 Basic Control */
153     #define GMII_RESET              ( 1 << 15 ) /* 1= Software Reset; 0=Normal Operation */
154     #define GMII_LOOPBACK           ( 1 << 14 ) /* 1=loopback Enabled; 0=Normal Operation */
155     #define GMII_SPEED_SELECT       ( 1 << 13 ) /* 1=100Mbps; 0=10Mbps */
156     #define GMII_AUTONEG            ( 1 << 12 ) /* Auto-negotiation Enable */
157     #define GMII_POWER_DOWN         ( 1 << 11 ) /* 1=Power down 0=Normal operation */
158     #define GMII_ISOLATE            ( 1 << 10 ) /* 1 = Isolates 0 = Normal operation */
159     #define GMII_RESTART_AUTONEG    ( 1 << 9 )  /* 1 = Restart auto-negotiation 0 = Normal operation */
160     #define GMII_DUPLEX_MODE        ( 1 << 8 )  /* 1 = Full duplex operation 0 = Normal operation */
161     #define GMII_COLLISION_TEST     ( 1 << 7 )  /* 1 = Enable COL test; 0 = Disable COL test */
162 /*#define GMII_SPEED_SELECT_MSB  (1 << 6)  // Reserved */
163 /*      Reserved                6 to 0   // Read as 0, ignore on write */
164 
165 /* Bit definitions: GMII_BMSR 0x01 Basic Status */
166     #define GMII_100BASE_T4       ( 1 << 15 ) /* 100BASE-T4 Capable */
167     #define GMII_100BASE_TX_FD    ( 1 << 14 ) /* 100BASE-TX Full Duplex Capable */
168     #define GMII_100BASE_T4_HD    ( 1 << 13 ) /* 100BASE-TX Half Duplex Capable */
169     #define GMII_10BASE_T_FD      ( 1 << 12 ) /* 10BASE-T Full Duplex Capable */
170     #define GMII_10BASE_T_HD      ( 1 << 11 ) /* 10BASE-T Half Duplex Capable */
171 /*      Reserved                10 to79  // Read as 0, ignore on write */
172 /*#define GMII_EXTEND_STATUS     (1 << 8)  // 1 = Extend Status Information In Reg 15 */
173 /*      Reserved                7 */
174     #define GMII_MF_PREAMB_SUPPR    ( 1 << 6 ) /* MII Frame Preamble Suppression */
175     #define GMII_AUTONEG_COMP       ( 1 << 5 ) /* Auto-negotiation Complete */
176     #define GMII_REMOTE_FAULT       ( 1 << 4 ) /* Remote Fault */
177     #define GMII_AUTONEG_ABILITY    ( 1 << 3 ) /* Auto Configuration Ability */
178     #define GMII_LINK_STATUS        ( 1 << 2 ) /* Link Status */
179     #define GMII_JABBER_DETECT      ( 1 << 1 ) /* Jabber Detect */
180     #define GMII_EXTEND_CAPAB       ( 1 << 0 ) /* Extended Capability */
181 
182 
183 /* Bit definitions: GMII_PHYID1 0x02 PHY Identifier 1 */
184 /* Bit definitions: GMII_PHYID2 0x03 PHY Identifier 2 */
185     #define GMII_LSB_MASK    0x3F
186     #define GMII_OUI_MSB     0x0022
187     #define GMII_OUI_LSB     0x05
188 
189 
190 /* Bit definitions: GMII_ANAR   0x04 Auto_Negotiation Advertisement */
191 /* Bit definitions: GMII_ANLPAR 0x05 Auto_negotiation Link Partner Ability */
192     #define GMII_NP               ( 1 << 15 ) /* Next page Indication */
193 /*      Reserved               7 */
194     #define GMII_RF               ( 1 << 13 ) /* Remote Fault */
195 /*      Reserved               12       // Write as 0, ignore on read */
196     #define GMII_PAUSE_MASK       ( 3 << 11 ) /* 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) */
197                                               /* 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) */
198     #define GMII_100T4            ( 1 << 9 )  /* 100BASE-T4 Support */
199     #define GMII_100TX_FDX        ( 1 << 8 )  /* 100BASE-TX Full Duplex Support */
200     #define GMII_100TX_HDX        ( 1 << 7 )  /* 100BASE-TX Support */
201     #define GMII_10_FDX           ( 1 << 6 )  /* 10BASE-T Full Duplex Support */
202     #define GMII_10_HDX           ( 1 << 5 )  /* 10BASE-T Support */
203 /*      Selector                 4 to 0   // Protocol Selection Bits */
204     #define GMII_AN_IEEE_802_3    0x0001      /* [00001] = IEEE 802.3 */
205 
206 
207 /* Bit definitions: GMII_ANER 0x06 Auto-negotiation Expansion */
208 /*      Reserved                15 to 5  // Read as 0, ignore on write */
209     #define GMII_PDF           ( 1 << 4 ) /* Local Device Parallel Detection Fault */
210     #define GMII_LP_NP_ABLE    ( 1 << 3 ) /* Link Partner Next Page Able */
211     #define GMII_NP_ABLE       ( 1 << 2 ) /* Local Device Next Page Able */
212     #define GMII_PAGE_RX       ( 1 << 1 ) /* New Page Received */
213     #define GMII_LP_AN_ABLE    ( 1 << 0 ) /* Link Partner Auto-negotiation Able */
214 
215 /**
216  * \brief Perform a HW initialization to the PHY and set up clocks.
217  *
218  * This should be called only once to initialize the PHY pre-settings.
219  * The PHY address is the reset status of CRS, RXD[3:0] (the GmacPins' pullups).
220  * The COL pin is used to select MII mode on reset (pulled up for Reduced MII).
221  * The RXDV pin is used to select test mode on reset (pulled up for test mode).
222  * The above pins should be predefined for corresponding settings in resetPins.
223  * The GMAC peripheral pins are configured after the reset is done.
224  *
225  * \param p_gmac   Pointer to the GMAC instance.
226  * \param uc_phy_addr PHY address.
227  * \param ul_mck GMAC MCK.
228  *
229  * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
230  */
231     uint8_t ethernet_phy_init( Gmac * p_gmac,
232                                uint8_t uc_phy_addr,
233                                uint32_t ul_mck );
234 
235 
236 /**
237  * \brief Get the Link & speed settings, and automatically set up the GMAC with the
238  * settings.
239  *
240  * \param p_gmac   Pointer to the GMAC instance.
241  * \param uc_phy_addr PHY address.
242  * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply.
243  *
244  * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
245  */
246     uint8_t ethernet_phy_set_link( Gmac * p_gmac,
247                                    uint8_t uc_phy_addr,
248                                    uint8_t uc_apply_setting_flag );
249 
250 
251 /**
252  * \brief Issue an auto negotiation of the PHY.
253  *
254  * \param p_gmac   Pointer to the GMAC instance.
255  * \param uc_phy_addr PHY address.
256  *
257  * Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
258  */
259     uint8_t ethernet_phy_auto_negotiate( Gmac * p_gmac,
260                                          uint8_t uc_phy_addr );
261 
262 /**
263  * \brief Issue a SW reset to reset all registers of the PHY.
264  *
265  * \param p_gmac   Pointer to the GMAC instance.
266  * \param uc_phy_addr PHY address.
267  *
268  * \Return GMAC_OK if successfully, GMAC_TIMEOUT if timeout.
269  */
270     uint8_t ethernet_phy_reset( Gmac * p_gmac,
271                                 uint8_t uc_phy_addr );
272 
273     typedef struct xPHY_PROPS
274     {
275         signed char phy_result;
276         uint32_t phy_params;
277         uint32_t phy_stat1;
278         uint32_t phy_stat2;
279         unsigned char phy_chn;
280     } PhyProps_t;
281     extern PhyProps_t phy_props;
282 
283     #ifdef __cplusplus
284 }         /* extern "C" */
285     #endif
286 
287 #endif /* #ifndef ETHERNET_PHY_H_INCLUDED */
288