Lines Matching refs:port
5 + Add ARMv7-R port with Memory Protection Unit (MPU) support.
6 + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
37 + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
39 + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
42 the MSP430F449 port to make it work with both MSP430 GCC and MSPGCC
47 + Update the POSIX port to pass the FreeRTOS task name to pthread for
49 + Update the POSIX port to ignore the user specified stack memory and only
53 + Update the POSIX port to use a timer thread for tick interrupts instead of
56 + Update ARM_TFM port to support TF-Mv2.0.0 release of trusted-firmware-m.
64 vApplicationGetTimerTaskMemory() in the RP2040 port. We thank @dpslwk for
69 + Fix compiler warnings in the MSP430F449 port when compiled with the
77 kernel common code and the kernel port code. We thank @barnatahmed for
98 + Add a template FreeRTOS port which can be used as a starting point for
99 developing a new FreeRTOS port.
143 + Add the port-optimized task selection algorithm optionally available for
155 + Fix stack end and stack size computation in POSIX port to meet the stack
167 + Fix vPortEndScheduler() for the MSVC port so that the function
261 + Add Cortex-M35P port. Contributed by @urutva.
262 + Add embedded extension (RV32E) support to the IAR RISC-V port.
295 + Fix build warning in MSP430X port when large data model is used.
296 + Add the ability to use Cortex-R5 port on the parts without FPU.
303 + Fix build issue in POSIX GCC port on Windows Subsystem for Linux (WSL). Contributed
305 + Add portMEMORY_BARRIER to Microblaze port. Contributed by @bbain.
306 + Add portPOINTER_SIZE_TYPE definition for ATmega port. Contributed by @jputcu.
349 + Add vectored mode interrupt support to the RISC-V port.
350 + Add support for RV32E extension (Embedded Profile) in RISC-V GCC port.
392 + Add hardware stack protection support to MicroBlazeV9 port. This ensures that
403 + Add prototype for prvPortYieldFromISR to the POSIX port so that it builds
435 + Update the RL78 IAR port to the latest version of IAR which uses the
438 + Add tick type is atomic flag when tick count is 16-bit to PIC24 port. This
443 + Remove #error when RISC-V port is compiled on a 64-bit RISC-V platform.
445 + Fix ullPortInterruptNesting alignment in Cortex-A53 port so that it is
450 + Change FreeRTOS IRQ Handler for Cortex-A53 SRE port to store and restore
451 interrupt acknowledge register. This ensures that the SRE port behavior
452 matches the Memory Mapped IO port. Contributed by @sviaunxp.
482 + ARMv8-M secure-side port: Tasks that call secure functions from the
524 + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from
526 + Correct a build error in the POSIX port.
560 + Add support for ESP IDF 4.2 to ThirdParty Xtensa port.
606 + New Renesas RXv3 port layer.
609 + Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in
610 the same way the Windows port layer enables FreeRTOS to run on Windows
629 + Added RISC-V port for the IAR compiler.
630 + Update the Windows simulator port to use a synchronous object to prevent
634 + Correct alignment of stack top in RISC-V port when
650 + Added contributed port and demo application for a T-Head (formally C-SKY)
677 + Added ARM Cortex-M23 port layer to complement the pre-existing ARM
678 Cortex-M33 port layer.
679 + The RISC-V port now automatically switches between 32-bit and 64-bit
698 + Added GCC RISC-V MCU port with three separate demo applications.
707 + Updated third party Xtensa port so it is MIT licensed.
709 compiler RX600v2 port to enable switching between platform.h and
710 iodefine.h includes within that port's port.c file.
759 + Added Xtensa port and demo application for the XCC compiler.
760 + Changed the implementation of vPortEndScheduler() for the Win32 port to
762 + Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect
830 in the MPU port.
840 + Improvements to the Win32 port including using higher priority threads.
842 + Updated GCC TriCore port to build with later compiler versions.
915 + Increase the priority of the Windows threads used by the Win32 port. As
918 prevent the Windows port executing on single core hosts.
932 + GCC ARM Cortex-A port: Introduced the configUSE_TASK_FPU_SUPPORT
935 + GCC ARM Cortex-A port: It is now possible to automatically save and
948 demonstrate how to use the updated MPU port.
955 + Add an ARM Cortex-M4F port for the MikroC compiler. Ensure to read the
956 documentation page for this port before use.
957 + MPS430X IAR port: Update to be compatible with the latest EW430 tools
959 + IAR32 GCC port: Correct vPortExitCritical() when
1040 Cortex-M3 port layers.
1048 + Added ARM Cortex-A53 64-bit port.
1049 + Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx
1066 + New PIC32MEC14xx port.
1068 port.
1069 + Zynq7000 port layer now declares the functions that setup and clear the
1073 + Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is
1074 currently the only port that uses it.
1075 + Updates to RL78 and 78K0 IAR port layers to improve support for
1101 + Added Intel IA32/x86 32-bit port.
1112 + Add additional NOPs to the MSP430X port layers to ensure strict compliance
1114 + Microblaze port: Added option for port optimised task selection.
1115 + Microblaze port: Previously tasks inherited the exception enable state
1118 + Windows port: Add additional safe guards to ensure the correct start up
1120 + Windows port: Improve the implementation of the port optimised task
1131 + Added demo project for the new IA32/x86 port that targets the Galileo
1150 + Improve the NetworkInterface.c file provided for the Windows port of
1161 + Some updates to the Xilinx Microblaze GCC port.
1162 + Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio.
1163 + Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a
1165 use the ARM Cortex-M4F port.
1168 Windows port.
1169 + Update the PIC32 port to remove deprecation warnings output by the latest
1229 + Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0
1231 + Cortex-A5 GIC-less port no longer passes the address of the interrupting
1244 + Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU.
1264 individual port layers where necessary so it does not affect ports that do
1300 + Fix a bug in the Tasking compiler's Cortex-M port that resulted in an
1306 + Updated the CCS Cortex-R4 port to enable it to be built with the latest
1313 + Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced.
1314 The new port is demonstrated on an Atmel SAMA5D3 XPlained board.
1394 + Add Cortex-A9 GCC port layer.
1420 + Added a port layer and a demo project for the new PIC32MZ architecture.
1421 + Update the PIC32MX port layer to re-introduce some ehb instructions that
1426 + Make dramatic improvements to the performance of the Win32 simulator port
1430 + Slight improvement to the Cortex-M4F port layers where previously one
1436 + Update the Cortex-M0 port layers to allow the scheduler to be started
1467 + Add Cortex-M0 port for Keil.
1468 + Updated Cortus port.
1520 Compatibility information for FreeRTOS port writers:
1555 + (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
1574 + Fix build error when R4 port is build in co-operative mode.
1575 + Multiple port and demo application maintenance activities.
1589 the yield macros of Cortex-M and Cortex-R port layers. For efficiency
1590 the Cortex-M port layer "yield" and "yield" from ISR are now implemented
1614 ARM Cortex-M3 port layers.
1620 + Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and
1628 + Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function
1635 + Minor optimisations to the PIC32 port layer.
1653 + Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to
1665 + Added port specific optimisations to the PIC32 port layer, and updated the
1667 + Added port specific optimisations to the Win32 simulator port.
1696 + Added a vQueueDelete() handler for the FreeRTOS MPU port (this was
1698 + Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to
1700 + Updated the prvReadGP() function in the NIOS II port to ensure the compiler
1722 used in the FreeRTOS MPU port.
1762 + Updated the FreeRTOS MPU port to be correct for changes that were
1766 + Tidy up various port implementations to add the static key word where
1773 + Changed the implementation of thread deletes in the Win32 port to prevent
1774 the port making use of the traceTASK_DELETE() trace macros - leaving this
1776 + Made some benign changes to the RX600 Renesas compiler port layer to
1814 + Cortex-M4F IAR port.
1815 + Cortex-M4F Keil/RVDS port.
1816 + TriCore GCC port.
1843 ports - including the new TriCore port where the checked pointer does not
1845 + The portCLEAN_UP_TCB() macro has been added to allow port specific clean
1846 up when a task is deleted - again this is required by the TriCore port.
1887 + The official FreeRTOS Renesas RX200 port and demo application have been
1889 + The official FreeRTOS Renesas RL78 port and demo application have been
1894 + A new Microblaze V8 port layer has been created to replace the older, now
1895 deprecated, port layer. The V8 port supports V8.x of the Microblaze IP,
1898 port layer. The demo application was created using V13.1 of the Xilinx
1917 not be retrofitted to existing ports until the existing port itself is
1924 + All ARM7 port layers have been slightly modified to prevent erroneous
1929 + The PIC32 port layer has been updated in preparation for V2 of the C32
1932 use the brand new Spartan-6 port and demo in its place.
1955 + Updated the RX600 port and demo applications to take into account the
1961 + Slightly changed the PIC32 port layer to move an ehb instruction in line
1989 + Updated the MSP430X IAR port and demo project to include support for the
1997 + Updated the PIC32 port layer to ensure the
2016 + Added a new port for the MSP430X core using the IAR Embedded Workbench.
2062 + Added port and demo application for the Cortus APS3 processor.
2079 + SuperH SH7216 (SH2A-FPU) port and demo application added.
2104 The following minor changes only effect the Cortex-M3 MPU port:
2160 + Added a new port and demo app for the Altera Nios2 soft core.
2180 + Added Virtex5 / PPC440 port and demos.
2192 + Added ColdFire V1 MCF51CN128 port and WEB server demo.
2194 + Changed the Cortex M3 port.c asm statements to __asm so it can be
2196 + Updated the Posix/Linux simulator contributed port.
2208 + Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a
2215 + Added in the lwIP port layer for the Coldfire MCF52259.
2235 PC port to instead use scheduler locks. This is because the BIOS calls
2241 + Added NEC V850ES port and demo.
2242 + Added NEC 78K0R port and demo.
2243 + Added MCF52259 port and demo.
2244 + Added the AT91SAM9XE port and demo.
2258 + Added IAR MSP430 port and demo.
2265 + Added a new port and demo application for the ColdFire V2 core using the
2268 Keil compiler with a new port that uses the new Keil/RVDS combo.
2273 + MSP430 port layers have been updated to permit tasks to place the
2276 + Replaced the two separate MSP430/Rowley port layers with a single and more
2284 + Completely re-written port for ColdFire GCC.
2297 ports and demos. See the port documentation pages on the FreeRTOS.org
2299 + Improved efficiency of Cortex M3 port even further.
2300 + Ensure the Cortex M3 port works no matter where the vector table is
2302 + Added the IntQTimer demo/test tasks to a demo project for each CM3 port
2318 + Updated the PIC32 port to allow queue API calls to be used from
2321 + Added a new PowerPC port that demonstrates how the trace macros can be
2326 + BUG FIX: The first PPC405 port contained a bug in that it did not leave
2368 + Efficiency gains within the PIC32 port layer.
2372 + Added a Virtex4 PowerPC 405 port and demo application.
2377 + Efficiency improvements to the Cortex-M3 port layer. NOTE: This
2383 M3 port layer (bringing it up to the same standard as the IAR and GCC
2390 + Added Fujitsu MB91460 port and demo.
2391 + Added Fujitsu MB96340 port and demo.
2404 + Updated STR9 uIP port to manually set the net mask and gateway addresses.
2450 + Updated the GCC port for the Cortex M3 to include the
2452 included in the IAR port.
2453 + Optimised the GCC and IAR port layer code - specifically the context
2464 + Updated the AVR32 port to ensure correct behaviour with full compiler
2466 + Included binaries for OpenOCD FTDI and parallel port interfaces.
2471 + Updated AVR32 UC3A port and demo applications.
2501 + Update to WizC PIC18 port to permit its use with version 14 of the
2519 + Added STR750 ARM7 port using the Raisonance RIDE/GCC tools.
2535 + Added STR750 port and demo.
2552 + Changed the critical section handling in the IAR AVR port to correct the
2579 + Added a port and demo application for the STR9 ARM9 based processors from
2587 + Added a port and demo application for the Cortex-M3 target using the IAR
2629 + Added a Luminary Micro port and demo for use with Rowley CrossWorks.
2636 + Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers.
2645 with every port:
2682 + GCC port now contain all assembler code in a single asm block rather than
2691 port.
2695 + Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above.
2697 + Added a new Microblaze port and demo application.
2722 + Added an IAR port for the Philips LPC2129
2749 One port just mirrors the existing GCC port. The other port was provided
2765 This release updates the HCS12 port. The common kernel code
2768 + Updated the HCS12 port to support banking and introduced a demo
2783 microcontrollers. Currently the HCS12 port is limited to the small
2786 + PIC18 wizC port updated. Thanks to Marcel van Lieshout for his
2788 + The accuracy of the AVR port timer setup has been improved. Thanks to
2810 + Each port now defines BaseType_t as the data type that is most
2820 + The AT91FR40008 ARM7 port contributed by John Feller is now included
2822 + The PIC18 port for the wizC/fedC compiler contributed by Marcel van
2824 + The IAR port for the AVR microcontroller has been upgraded to V3.0.0
2825 and is now a supported port.
2836 accommodate the wizC/fedC PIC port.
2839 directory and the IAR port in the Demo/AVR_ATMega323_IAR directory.
2849 specifically to the port being used. The application specific
2854 the demo application rather than being specific to the port.
2866 + The portheap.c file included with the AVR port has been deleted. The
2868 + The GCC AVR port is now build using the standard make utility. The
2891 + The MPLAB PIC port now saved the TABLAT register in interrupt service
2903 + AVR port - Replaced the inb() and outb() functions with direct memory
2904 access. This allows the port to be built with the 20050414 build of
2906 + GCC LPC2106 port - removed the 'static' from the definition of
2909 + GCC LPC2106 port - Corrected the optimisation options in the batch files
2968 port. Some optimisation levels use the stack differently to others. This
2971 tasks context. This allows the GCC ARM7 port to be used at all
2981 + Added the Keil ARM7 port.
2987 + Added the MSP430 port.
2988 + Extra comments added to the GCC ARM7 port.c and portISR.c files.
3019 + The ARM7 port now supports THUMB mode.
3020 + Modification to the ARM7 demo application serial port driver.
3024 + Rationalised the ARM7 port version of portEXIT_CRITICAL() -
3031 + Added the first ARM7 port - thanks to Bill Knight for the assistance
3047 + Added an AVR port that uses the IAR compiler.
3059 + Added Cygnal 8051 port.
3064 + Minor changes to prevent compiler warnings when compiling the new port.
3135 Barring the change to the interrupt vector (PIC port) these are minor
3147 + Reverted the Flashlite COM port driver back so it does not use the DMA.
3149 port was also calculating a register value incorrectly resulting in the
3160 Small fix made to the PIC specific port.c file described below.
3169 V1.2.4 contains a release version of the PIC18 port.
3185 + The ATMega port definition of portCPU_CLOSK_HZ definition changed to
3195 The zip file also contains a pre-release version of the PIC18 port. This
3203 portSTACK_GROWTH macro. This is required for the PIC port where the
3207 where it should have been since the creation of an eight bit port.
3222 files specific to the Borland compiler port.
3225 transmitted and received on the serial port. The Flashlite 186 demo
3241 The Flashlite 186 serial port driver has also been modified to use a DMA
3275 The majority of these changes were made to accommodate the 8bit AVR port.
3282 + Added AVR port.
3313 + Minor change to the Flashlite serial port driver. The driver is written
3349 + The Flashlite 186 port now uses 186 instruction set (used to use 80x86
3358 seems to have problems stepping over the call. This if for the PC port