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20 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
21 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
31 XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
33 Xtensa low level exception and interrupt vectors and handlers for an RTOS.
40 Users can install application-specific interrupt handlers for low and
52 '-DXT_INTEXC_HOOKS' (useful for automated testing).
55 !! application specific interrupts. Search USER_EDIT for helpful comments !!
60 provided for each exception type. Note that some exceptions are handled
77 defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
79 For example, this file provides interrupt vector templates for all types and
82 NOTES on the use of 'call0' for long jumps instead of 'j':
94 live at the time of the call, which is always the case for a function
150 NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
154 mask -- interrupt bitmask for this level
249 j .L_xt_user_int_&level& /* check for more interrupts */
257 Interrupt handler for the RTOS tick timer if at this level.
275 j .L_xt_user_int_&level& /* check for more interrupts */
333 Hooks to dynamically install handlers for exceptions and interrupts.
336 with index 0 containing the entry for user exceptions.
338 See comment in xtensa_rtos.h for more details.
368 calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
497 Insert some waypoints for jumping beyond the signed 8-bit range of
555 /* NOTE: we'll stay on the user stack for exception handling. */
562 s32e a0, sp, -12 /* for debug backtrace */
571 s32e a0, sp, -16 /* for debug backtrace */
583 /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
593 rsr a0, EPC_1 /* return address for debug backtrace */
595 rsync /* wait for WSR.PS to complete */
599 rsync /* wait for WSR.PS to complete */
654 Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
688 Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
689 Use a minimal stack frame (16B) to save A2 & A3 for scratch.
703 For this reason, a full interrupt stack frame is allocated.
763 /* Bitmask for CP n's CPENABLE bit. */
810 s32e a0, sp, -12 /* for debug backtrace */
819 s32e a0, sp, -16 /* for debug backtrace */
821 movi a0, _xt_user_exit /* save exit point for dispatch */
843 movi a3, _xt_coproc_owner_sa /* (placed here for load slot) */
883 add a2, a2, a5 /* a2 = old owner's area for CP n */
887 It is theoretically possible for Xtensa processor designers to write TIE
895 /* Check if any state has to be restored for new owner. */
904 /* Adjust new owner's save area pointers to area for CP n. */
909 add a2, a4, a5 /* a2 = new owner's area for CP */
913 It is theoretically possible for Xtensa processor designers to write TIE
921 /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */
980 movi a0, _xt_user_exit /* save exit point for dispatch */
988 /* Set up PS for C, enable interrupts above this level and clear EXCM. */
1011 setting PS.EXCM and therefore can easily support a C environment for
1024 calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
1062 movi a0, _xt_medint2_exit /* save exit point for dispatch */
1070 /* Set up PS for C, enable interrupts above this level and clear EXCM. */
1087 Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
1135 movi a0, _xt_medint3_exit /* save exit point for dispatch */
1143 /* Set up PS for C, enable interrupts above this level and clear EXCM. */
1160 Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
1207 movi a0, _xt_medint4_exit /* save exit point for dispatch */
1215 /* Set up PS for C, enable interrupts above this level and clear EXCM. */
1232 Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
1279 movi a0, _xt_medint5_exit /* save exit point for dispatch */
1287 /* Set up PS for C, enable interrupts above this level and clear EXCM. */
1304 Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
1351 movi a0, _xt_medint6_exit /* save exit point for dispatch */
1359 /* Set up PS for C, enable interrupts above this level and clear EXCM. */
1376 Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
1411 and used for purposes requiring very short service times.
1413 Here are templates for high priority (level 2+) interrupt vectors.
1415 which interrupts at this level are pending and enabled. This allows for
1429 Currently only shells for high priority interrupt handlers are provided
1678 Here is the code for each window overflow/underflow exception vector and
1679 (interspersed) efficient code for handling the alloca exception cause.
1681 tight for performance. The alloca exception is also handled entirely in
1692 These things are coded for XEA2 only (XEA1 is not supported).
1695 The underflow handler for returning from call[i+1] to call[i]
1710 Window Overflow Exception for Call4.
1735 Window Underflow Exception for Call4
1766 handler, so those 4 registers are available for scratch.
1794 Window Overflow Exception for Call8
1825 Window Underflow Exception for Call8
1856 Window Overflow Exception for Call12
1891 Window Underflow Exception for Call12