Lines Matching full:0
50 …_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h …
58 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
59 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
60 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
61 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
62 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
63 #define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
68 #define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
69 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
70 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
73 #define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
74 #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
75 #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
76 #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
78 #define portMPU_ENABLE ( 0x01UL )
80 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
81 #define portMPU_REGION_VALID ( 0x10UL )
82 #define portMPU_REGION_ENABLE ( 0x01UL )
83 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
84 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
87 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
88 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
89 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
95 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Float…
96 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
99 #define portINITIAL_XPSR ( 0x01000000UL )
100 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
101 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
102 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
105 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
111 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
112 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
113 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
114 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
116 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
129 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
130 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
141 #define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
150 PRIVILEGED_DATA static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
152 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
217 static uint8_t ucMaxSysCallPriority = 0;
218 static uint32_t ulMaxPRIGROUPValue = 0;
225 * @return 1 if the processor is already privileged, 0 otherwise.
230 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
233 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
234 * Bit[0] = 0 --> The processor is running privileged
235 * Bit[0] = 1 --> The processor is running unprivileged.
262 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
269 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
271 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
285 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
287 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
294 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
296 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
308 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
330 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED; in pxPortInitialiseStack()
335 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; in pxPortInitialiseStack()
338 xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ in pxPortInitialiseStack()
339 xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ in pxPortInitialiseStack()
340 xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ in pxPortInitialiseStack()
341 xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ in pxPortInitialiseStack()
342 xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ in pxPortInitialiseStack()
343 xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ in pxPortInitialiseStack()
344 xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ in pxPortInitialiseStack()
345 xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ in pxPortInitialiseStack()
350 xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ in pxPortInitialiseStack()
351 xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ in pxPortInitialiseStack()
352 xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ in pxPortInitialiseStack()
353 xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ in pxPortInitialiseStack()
354 xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ in pxPortInitialiseStack()
358 #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) in pxPortInitialiseStack()
368 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ in pxPortInitialiseStack()
389 * argument (r0) is pulParam[ 0 ]. */ in vSVCHandler_C()
451 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
464 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
467 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
499 ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) in vSystemCallEnter()
503 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) in vSystemCallEnter()
519 for( i = 0; i < ulStackFrameSize; i++ ) in vSystemCallEnter()
572 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
575 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
584 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
587 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
617 if( ( ulLR & portEXC_RETURN_STACK_FRAME_TYPE_MASK ) == 0UL ) in vSystemCallExit()
633 for( i = 0; i < ulStackFrameSize; i++ ) in vSystemCallExit()
675 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
692 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
726 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
749 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
757 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */ in prvRestoreContextOfFirstTask()
768 ldr r0, =0xe000ed94 /* MPU_CTRL register. */ in prvRestoreContextOfFirstTask()
770 bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ in prvRestoreContextOfFirstTask()
773 ldr r0, =0xe000ed9c /* Region Base Address register. */ in prvRestoreContextOfFirstTask()
774 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ in prvRestoreContextOfFirstTask()
775 stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ in prvRestoreContextOfFirstTask()
784 ldr r0, =0xe000ed94 /* MPU_CTRL register. */ in prvRestoreContextOfFirstTask()
786 orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ in prvRestoreContextOfFirstTask()
802 mov r0, #0 in prvRestoreContextOfFirstTask()
814 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. in xPortStartScheduler()
840 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct in xPortStartScheduler()
868 volatile uint32_t ulImplementedPrioBits = 0; in xPortStartScheduler()
892 * hardware. A priority of 0 is invalid because setting the BASEPRI in xPortStartScheduler()
893 * register to 0 unmasks all interrupts, and interrupts with priority 0 in xPortStartScheduler()
900 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); in xPortStartScheduler()
908 ucMaxPriorityValue <<= ( uint8_t ) 0x01; in xPortStartScheduler()
930 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); in xPortStartScheduler()
931 ulMaxPRIGROUPValue = 0; in xPortStartScheduler()
954 portNVIC_SHPR2_REG = 0; in xPortStartScheduler()
964 uxCriticalNesting = 0; in xPortStartScheduler()
966 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) in xPortStartScheduler()
982 return 0; in xPortStartScheduler()
992 ldr r0, =0xE000ED08 in prvStartFirstTask()
1002 mov r0, #0 in prvStartFirstTask()
1061 if( uxCriticalNesting == 0 ) in vPortExitCritical()
1076 if( uxCriticalNesting == 0 ) in vPortExitCritical()
1085 if( uxCriticalNesting == 0 ) in vPortExitCritical()
1111 add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */ in xPortPendSVHandler()
1112 tst lr, #0x10 in xPortPendSVHandler()
1117 sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */ in xPortPendSVHandler()
1136 mov r0, #0 in xPortPendSVHandler()
1145 ldr r0, =0xe000ed94 /* MPU_CTRL register. */ in xPortPendSVHandler()
1147 bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ in xPortPendSVHandler()
1150 ldr r0, =0xe000ed9c /* Region Base Address register. */ in xPortPendSVHandler()
1151 ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ in xPortPendSVHandler()
1152 stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ in xPortPendSVHandler()
1161 ldr r0, =0xe000ed94 /* MPU_CTRL register. */ in xPortPendSVHandler()
1163 orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ in xPortPendSVHandler()
1178 tst lr, #0x10 in xPortPendSVHandler()
1220 portNVIC_SYSTICK_CTRL_REG = 0UL; in vSetupTimerInterrupt()
1221 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; in vSetupTimerInterrupt()
1234 ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */ in vPortEnableVFP()
1237 orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */ in vPortEnableVFP()
1347 …movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ in xIsPrivileged()
1348 moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ in xIsPrivileged()
1397 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = in vPortStoreTaskMPUSettings()
1402 xMPUSettings->xRegion[ 0 ].ulRegionAttribute = in vPortStoreTaskMPUSettings()
1409 … xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__; in vPortStoreTaskMPUSettings()
1410 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__; in vPortStoreTaskMPUSettings()
1411 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | in vPortStoreTaskMPUSettings()
1418 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; in vPortStoreTaskMPUSettings()
1419 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; in vPortStoreTaskMPUSettings()
1420 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; in vPortStoreTaskMPUSettings()
1421 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; in vPortStoreTaskMPUSettings()
1430 if( ulStackDepth > 0 ) in vPortStoreTaskMPUSettings()
1433 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = in vPortStoreTaskMPUSettings()
1438 xMPUSettings->xRegion[ 0 ].ulRegionAttribute = in vPortStoreTaskMPUSettings()
1445 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; in vPortStoreTaskMPUSettings()
1446 …xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfSt… in vPortStoreTaskMPUSettings()
1448 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | in vPortStoreTaskMPUSettings()
1452 lIndex = 0; in vPortStoreTaskMPUSettings()
1456 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) in vPortStoreTaskMPUSettings()
1473 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; in vPortStoreTaskMPUSettings()
1490 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; in vPortStoreTaskMPUSettings()
1491 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; in vPortStoreTaskMPUSettings()
1492 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; in vPortStoreTaskMPUSettings()
1493 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; in vPortStoreTaskMPUSettings()
1522 for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) in xPortIsAuthorizedToAccessBuffer()
1605 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the in vPortValidateInterruptPriority()
1615 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1631 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1634 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1650 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1653 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1684 …AccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) in xPortIsAuthorizedToAccessKernelObject()
1707 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */