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30 * Implementation of functions defined in portable.h for the ARM CM3 port.
42  * replace the function that configures the clock used to generate the tick
43  * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
44  * the application writer can override it by simply defining a function of the
50 /* Constants required to manipulate the core.  Registers first... */
55 /* ...then bits in the registers. */
68 /* Constants required to check the validity of an interrupt priority. */
78 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
81 /* Constants required to set up the initial stack. */
84 /* The systick is a 24-bit counter. */
87 /* A fiddle factor to estimate the number of SysTick counts that would have
88  * occurred while the SysTick counter is stopped during tickless idle
92 /* For strict compliance with the Cortex-M spec the task start address should
93  * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
96 /* Let the user override the default SysTick clock rate.  If defined by the
97  * user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
101     /* Ensure the SysTick is clocked at the same frequency as the core. */
104     /* Select the option to clock SysTick not at the same frequency as the core. */
109  * Setup the timer to generate the tick interrupts.  The implementation in this
110  * file is weak to allow application writers to change the timer used to
111  * generate the tick interrupt.
134 /* Each task maintains its own interrupt status in the critical nesting
139  * The number of SysTick increments that make up one tick period.
146  * The maximum number of tick periods that can be suppressed is limited by the
147  * 24 bit resolution of the SysTick timer.
154  * Compensate for the CPU cycles that pass while the SysTick is stopped (low
162  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
181     /* Simulate the stack frame as it would be created by a context switch  in pxPortInitialiseStack()
183 …                                 /* Offset added to account for the way the MCU uses the stack on …  in pxPortInitialiseStack()
205      * defined, then stop here so application writers can catch the error. */  in prvTaskExitError()
220     ldr r3, = pxCurrentTCB   /* Restore the context. */  in vPortSVCHandler()
221     ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */  in vPortSVCHandler()
222     ldr r0, [ r1 ]           /* The first item in pxCurrentTCB is the task top of stack. */  in vPortSVCHandler()
223 …ldmia r0 !, { r4 - r11 } /* Pop the registers that are not automatically saved on exception entry …  in vPortSVCHandler()
224     msr psp, r0 /* Restore the task stack pointer. */  in vPortSVCHandler()
239     /* Use the NVIC offset register to locate the stack. */  in prvStartFirstTask()
244     /* Set the msp back to the start of the stack. */  in prvStartFirstTask()
251     /* Call SVC to start the first task. */  in prvStartFirstTask()
271         /* Determine the maximum priority from which ISR safe FreeRTOS API  in xPortStartScheduler()
276          * Save the interrupt priority value that is about to be clobbered. */  in xPortStartScheduler()
279         /* Determine the number of priority bits available.  First write to all  in xPortStartScheduler()
283         /* Read the value back to see how many bits stuck. */  in xPortStartScheduler()
286         /* Use the same mask on the maximum system call priority. */  in xPortStartScheduler()
289         /* Check that the maximum system call priority is nonzero after  in xPortStartScheduler()
290          * accounting for the number of priority bits supported by the  in xPortStartScheduler()
291          * hardware. A priority of 0 is invalid because setting the BASEPRI  in xPortStartScheduler()
297         /* Check that the bits not implemented in hardware are zero in  in xPortStartScheduler()
301         /* Calculate the maximum acceptable priority group value for the number  in xPortStartScheduler()
312             /* When the hardware implements 8 priority bits, there is no way for  in xPortStartScheduler()
313              * the software to configure PRIGROUP to not have sub-priorities. As  in xPortStartScheduler()
314              * a result, the least significant bit is always used for sub-priority  in xPortStartScheduler()
320              * are at the same preemption priority. This may appear confusing as  in xPortStartScheduler()
324              * to 4, this confusion does not happen and the behaviour remains the same.  in xPortStartScheduler()
326              * The following assert ensures that the sub-priority bit in the  in xPortStartScheduler()
327              * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned  in xPortStartScheduler()
337         /* Shift the priority group value back to its position within the AIRCR  in xPortStartScheduler()
342         /* Restore the clobbered interrupt priority register to its original  in xPortStartScheduler()
348     /* Make PendSV and SysTick the lowest priority interrupts. */  in xPortStartScheduler()
353     /* Start the timer that generates the tick ISR.  Interrupts are disabled  in xPortStartScheduler()
357     /* Initialise the critical nesting count ready for the first task. */  in xPortStartScheduler()
360     /* Start the first task. */  in xPortStartScheduler()
381     /* This is not the interrupt safe version of the enter critical function so  in vPortEnterCritical()
384      * the critical nesting count is 1 to protect against recursive calls if the  in vPortEnterCritical()
417     ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */  in xPortPendSVHandler()
420     stmdb r0 !, { r4 - r11 } /* Save the remaining registers. */  in xPortPendSVHandler()
421     str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */  in xPortPendSVHandler()
434     ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */  in xPortPendSVHandler()
435     ldmia r0 !, { r4 - r11 } /* Pop the registers and the critical nesting count. */  in xPortPendSVHandler()
446     /* The SysTick runs at the lowest interrupt priority, so when this interrupt  in xPortSysTickHandler()
448      * save and then restore the interrupt mask value as its value is already  in xPortSysTickHandler()
449      * known - therefore the slightly faster vPortRaiseBASEPRI() function is used  in xPortSysTickHandler()
454         /* Increment the RTOS tick. */  in xPortSysTickHandler()
460              * the PendSV interrupt.  Pend the PendSV interrupt. */  in xPortSysTickHandler()
480         /* Make sure the SysTick reload value does not overflow the counter. */  in vPortSuppressTicksAndSleep()
486         /* Enter a critical section but don't use the taskENTER_CRITICAL()  in vPortSuppressTicksAndSleep()
492         /* If a context switch is pending or a task is waiting for the scheduler  in vPortSuppressTicksAndSleep()
493          * to be unsuspended then abandon the low power entry. */  in vPortSuppressTicksAndSleep()
496             /* Re-enable interrupts - see comments above the __disable_irq()  in vPortSuppressTicksAndSleep()
502             /* Stop the SysTick momentarily.  The time the SysTick is stopped for  in vPortSuppressTicksAndSleep()
503              * is accounted for as best it can be, but using the tickless mode will  in vPortSuppressTicksAndSleep()
504              * inevitably result in some tiny drift of the time maintained by the  in vPortSuppressTicksAndSleep()
508             /* Use the SysTick current-value register to determine the number of  in vPortSuppressTicksAndSleep()
509              * SysTick decrements remaining until the next tick interrupt.  If the  in vPortSuppressTicksAndSleep()
511              * ulTimerCountsForOneTick decrements remaining, not zero, because the  in vPortSuppressTicksAndSleep()
512              * SysTick requests the interrupt when decrementing from 1 to 0. */  in vPortSuppressTicksAndSleep()
520             /* Calculate the reload value required to wait xExpectedIdleTime  in vPortSuppressTicksAndSleep()
522              * way through the first tick period.  But if the SysTick IRQ is now  in vPortSuppressTicksAndSleep()
523              * pending, then clear the IRQ, suppressing the first tick, and correct  in vPortSuppressTicksAndSleep()
524              * the reload value to reflect that the second tick period is already  in vPortSuppressTicksAndSleep()
525              * underway.  The expected idle time is always at least two ticks. */  in vPortSuppressTicksAndSleep()
539             /* Set the new reload value. */  in vPortSuppressTicksAndSleep()
542             /* Clear the SysTick count flag and set the count value back to  in vPortSuppressTicksAndSleep()
552              * should not be executed again.  However, the original expected idle  in vPortSuppressTicksAndSleep()
566             /* Re-enable interrupts to allow the interrupt that brought the MCU  in vPortSuppressTicksAndSleep()
568              * the __disable_irq() call above. */  in vPortSuppressTicksAndSleep()
573             /* Disable interrupts again because the clock is about to be stopped  in vPortSuppressTicksAndSleep()
574              * and interrupts that execute while the clock is stopped will increase  in vPortSuppressTicksAndSleep()
575              * any slippage between the time maintained by the RTOS and calendar  in vPortSuppressTicksAndSleep()
581             /* Disable the SysTick clock without reading the  in vPortSuppressTicksAndSleep()
582              * portNVIC_SYSTICK_CTRL_REG register to ensure the  in vPortSuppressTicksAndSleep()
584              * the time the SysTick is stopped for is accounted for as best it can  in vPortSuppressTicksAndSleep()
585              * be, but using the tickless mode will inevitably result in some tiny  in vPortSuppressTicksAndSleep()
586              * drift of the time maintained by the kernel with respect to calendar  in vPortSuppressTicksAndSleep()
590             /* Determine whether the SysTick has already counted to zero. */  in vPortSuppressTicksAndSleep()
595                 /* The tick interrupt ended the sleep (or is now pending), and  in vPortSuppressTicksAndSleep()
597                  * with whatever remains of the new tick period. */  in vPortSuppressTicksAndSleep()
601                  * underflowed because the post sleep hook did something  in vPortSuppressTicksAndSleep()
602                  * that took too long or because the SysTick current-value register  in vPortSuppressTicksAndSleep()
611                 /* As the pending tick will be processed as soon as this  in vPortSuppressTicksAndSleep()
612                  * function exits, the tick value maintained by the tick is stepped  in vPortSuppressTicksAndSleep()
613                  * forward by one less than the time spent waiting. */  in vPortSuppressTicksAndSleep()
618                 /* Something other than the tick interrupt ended the sleep. */  in vPortSuppressTicksAndSleep()
620                 /* Use the SysTick current-value register to determine the  in vPortSuppressTicksAndSleep()
621                  * number of SysTick decrements remaining until the expected idle  in vPortSuppressTicksAndSleep()
626                     /* If the SysTick is not using the core clock, the current-  in vPortSuppressTicksAndSleep()
627                      * value register might still be zero here.  In that case, the  in vPortSuppressTicksAndSleep()
628                      * SysTick didn't load from the reload register, and there are  in vPortSuppressTicksAndSleep()
629                      * ulReloadValue decrements remaining in the expected idle  in vPortSuppressTicksAndSleep()
638                 /* Work out how long the sleep lasted rounded to complete tick  in vPortSuppressTicksAndSleep()
639                  * periods (not the ulReload value which accounted for part  in vPortSuppressTicksAndSleep()
643                 /* How many complete tick periods passed while the processor  in vPortSuppressTicksAndSleep()
647                 /* The reload value is set to whatever fraction of a single tick  in vPortSuppressTicksAndSleep()
654              * the SysTick is not using the core clock, temporarily configure it to  in vPortSuppressTicksAndSleep()
655              * use the core clock.  This configuration forces the SysTick to load  in vPortSuppressTicksAndSleep()
656              * from portNVIC_SYSTICK_LOAD_REG immediately instead of at the next  in vPortSuppressTicksAndSleep()
657              * cycle of the other clock.  Then portNVIC_SYSTICK_LOAD_REG is ready  in vPortSuppressTicksAndSleep()
658              * to receive the standard value immediately. */  in vPortSuppressTicksAndSleep()
667                 /* The temporary usage of the core clock has served its purpose,  in vPortSuppressTicksAndSleep()
668                  * as described above.  Resume usage of the other clock. */  in vPortSuppressTicksAndSleep()
673                     /* The partial tick period already ended.  Be sure the SysTick  in vPortSuppressTicksAndSleep()
683             /* Step the tick to account for any tick periods that elapsed. */  in vPortSuppressTicksAndSleep()
696  * Setup the SysTick timer to generate the tick interrupts at the required
703         /* Calculate the constants required to configure the tick interrupt. */  in vPortSetupTimerInterrupt()
712         /* Stop and clear the SysTick. */  in vPortSetupTimerInterrupt()
716         /* Configure SysTick to interrupt at the requested rate. */  in vPortSetupTimerInterrupt()
742         /* Obtain the number of the currently executing interrupt. */  in vPortValidateInterruptPriority()
745         /* Is the interrupt number a user defined interrupt? */  in vPortValidateInterruptPriority()
748             /* Look up the interrupt's priority. */  in vPortValidateInterruptPriority()
751             /* The following assertion will fail if a service routine (ISR) for  in vPortValidateInterruptPriority()
759              * interrupt priorities, therefore the priority of the interrupt must  in vPortValidateInterruptPriority()
763              * Interrupts that  use the FreeRTOS API must not be left at their  in vPortValidateInterruptPriority()
764              * default priority of  zero as that is the highest possible priority,  in vPortValidateInterruptPriority()
771              * The following links provide detailed information:  in vPortValidateInterruptPriority()
777         /* Priority grouping:  The interrupt controller (NVIC) allows the bits  in vPortValidateInterruptPriority()
779          * define the interrupt's pre-emption priority bits and bits that define  in vPortValidateInterruptPriority()
780          * the interrupt's sub-priority.  For simplicity all bits must be defined  in vPortValidateInterruptPriority()
781          * to be pre-emption priority bits.  The following assertion will fail if  in vPortValidateInterruptPriority()
782          * this is not the case (if some bits represent a sub-priority).  in vPortValidateInterruptPriority()
784          * If the application only uses CMSIS libraries for interrupt  in vPortValidateInterruptPriority()
785          * configuration then the correct setting can be achieved on all Cortex-M  in vPortValidateInterruptPriority()
786          * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the  in vPortValidateInterruptPriority()