Lines Matching full:for
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
44 * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
49 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
54 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
69 …ed. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIM…
123 …Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for …
137 add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
147 * for the function is as per the other ports:
154 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
216 addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
217 store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
219 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-15. */
221 addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
224 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
230 addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
244 …load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the…
276 …L_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task…
278 store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
292 csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
293 csrr t1, CSR_MEPC /* For viewing in the debugger only */
294 csrr t2, CSR_MSTATUS /* For viewing in the debugger only */
299 csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
300 csrr t1, CSR_MEPC /* For viewing in the debugger only */
301 csrr t2, CSR_MSTATUS /* For viewing in the debugger only */