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242 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
243 #define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority …
244 #define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest pr…
245 #define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest p…
246 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt…
247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal …
248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External …
249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal …
250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External …
251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal …
252 #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal …
253 /* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
254 #define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Stat…
255 #define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Stat…
256 /* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
257 #define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protectio…
258 #define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General M…
277 /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
278 #define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
279 #define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
280 #define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
281 #define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
282 /* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
315 /* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
316 #define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
317 #define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */
318 #define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */
319 #define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
320 #define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable …
321 #define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable…
322 #define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */
323 /* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
324 #define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */
325 #define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */
326 #define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */
327 #define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 …
328 #define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 …
329 #define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */
330 #define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */
331 #define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
332 #define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The US…
333 #define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Rec…
334 #define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Tra…
335 #define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RX…
336 /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
337 #define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
338 #define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
339 #define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Tran…
340 #define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Int…
341 #define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
342 #define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Inter…
343 #define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interr…
344 #define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
345 #define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
346 #define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
347 #define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
348 #define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
349 /* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
350 /* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
351 /* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
352 /* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
353 #define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
409 /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
410 #define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Ena…
411 #define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Byp…
412 #define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Sta…
413 /* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
414 #define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequenc…
415 #define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */
416 /* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
417 #define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */
418 #define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0…
419 #define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed…
420 #define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */
421 #define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequenc…
422 #define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the…
423 #define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the…
424 #define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the…
425 #define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the…
426 #define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
427 #define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clo…
428 #define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is P…
429 #define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is P…
430 #define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is P…
459 /* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
460 #define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */
461 #define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */
462 #define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */
463 #define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */
464 #define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
465 #define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
466 /* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
467 /* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
468 /* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
469 /* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
470 /* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
471 /* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
472 #define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Sel…
473 #define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected…
474 #define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected…
475 #define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is sele…
476 #define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Pre…
477 #define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
478 #define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided…
479 #define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided…
480 #define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided…
481 #define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided…
482 #define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided…
483 #define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided…
484 /* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
485 /* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
486 #define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Di…
487 #define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Dis…
488 #define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable…
489 #define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enabl…
490 #define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enabl…
491 #define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enabl…
492 #define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enabl…
493 /* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
494 /* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
495 /* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
507 /* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
508 #define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset…
509 #define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Rese…
510 #define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset …
511 #define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
512 /* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
513 #define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Stat…
514 #define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detect…
515 #define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */
516 #define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset.…
517 #define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. V…
518 #define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset.…
519 #define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset.…
520 #define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRS…
521 #define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset …
522 #define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level …
523 #define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset …
524 /* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
525 #define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enab…
526 #define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Inte…
527 #define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enab…
528 #define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detect…
541 /* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
542 #define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescale…
543 #define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
544 #define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Incremen…
545 #define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart …
546 /* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
547 #define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */
548 /* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
549 #define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value …
550 /* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
551 #define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
552 #define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Incremen…
565 /* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
566 #define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
567 #define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer En…
568 #define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer In…
569 /* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
570 #define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer St…
571 /* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
572 #define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval …
573 #define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter …
574 /* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
586 /* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
587 #define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */
588 #define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
589 /* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
590 #define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
591 #define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt…
592 #define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
593 #define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
594 #define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */
595 #define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
596 #define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
597 #define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
598 /* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
599 #define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
600 #define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */
610 /* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
611 #define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standb…
627 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
628 #define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bi…
629 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
630 #define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess…
631 #define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addes…
632 #define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Statu…
633 #define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
634 #define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
635 #define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */
636 #define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Statu…
637 #define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */
638 #define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */
639 #define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */
640 #define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort S…
641 #define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort S…
642 #define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 A…
643 #define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 A…
644 /* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
645 #define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */
646 #define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
647 #define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Erro…
648 #define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before …
649 #define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State…
650 #define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read…
651 #define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Rea…
652 #define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Rea…
653 #define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Rea…
654 #define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecon…
655 /* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
656 #define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */
657 #define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the progr…
658 #define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock se…
659 #define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequenc…
660 #define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock…
661 #define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase…
662 #define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purp…
663 #define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Pu…
664 #define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit…
665 #define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
666 #define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect …
667 /* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
668 #define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Sta…
669 #define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock St…
670 #define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock St…
671 #define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock St…
672 #define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock St…
673 #define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock St…
674 #define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock St…
675 #define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock St…
676 #define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock St…
677 #define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock St…
678 #define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock St…
679 #define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock St…
680 #define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock St…
681 #define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock St…
682 #define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock St…
683 #define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock St…
684 #define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock St…
685 #define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock St…
686 #define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock St…
687 #define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock S…
688 #define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock S…
689 #define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock S…
690 #define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock S…
691 #define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock S…
692 #define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock S…
722 /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
723 #define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */
724 #define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */
725 #define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */
726 #define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */
727 /* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
728 #define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */
729 #define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */
730 #define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Sel…
731 #define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral …
732 #define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
733 #define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */
734 #define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection…
735 #define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */
736 #define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Sele…
737 #define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip S…
738 /* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
739 #define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
740 #define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Sele…
741 /* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
742 #define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
743 #define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Sele…
744 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
745 #define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Registe…
746 #define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Regist…
747 #define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
748 #define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status…
749 #define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Tran…
750 #define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Tran…
751 #define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
752 #define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
753 #define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */
754 #define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
755 #define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */
756 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
757 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
758 /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
759 /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
760 #define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */
761 #define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */
762 #define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After …
763 #define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */
764 #define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
765 #define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
766 #define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
767 #define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
768 #define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
769 #define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
770 #define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
771 #define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
772 #define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
773 #define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
774 #define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
775 #define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive…
811 /* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
812 #define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */
813 #define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
814 #define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
815 #define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
816 #define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations…
817 #define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknow…
818 #define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
819 #define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal re…
820 #define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal re…
821 #define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send …
822 #define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send …
823 /* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
824 #define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */
825 #define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */
826 #define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */
827 #define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handsha…
828 #define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */
829 … AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = …
830 #define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol…
831 #define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */
832 #define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handsha…
833 #define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection …
834 #define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */
835 #define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */
836 #define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM)…
837 #define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */
838 #define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection …
839 #define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length…
840 #define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length…
841 #define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length…
842 #define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length…
843 #define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode…
844 #define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop b…
845 #define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
846 …ne AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0…
847 #define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
848 #define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
849 #define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character …
850 #define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Sel…
851 #define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mo…
852 #define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Ackn…
853 #define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successi…
854 #define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repeti…
855 #define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Fil…
856 /* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
857 #define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/E…
858 #define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-ou…
859 #define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Re…
860 #define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge …
861 #define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator I…
862 #define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready I…
863 #define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Fla…
864 #define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send In…
865 /* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
866 /* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
867 /* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
868 #define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */
869 #define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */
870 #define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */
871 #define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */
908 /* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
909 #define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */
910 #define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable …
911 #define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable …
912 #define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable…
913 #define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */
914 /* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
915 #define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit…
916 #define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */
917 #define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal …
918 #define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */
919 #define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit…
920 #define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit…
921 #define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Recei…
922 #define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit…
923 #define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit…
924 #define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit…
925 #define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as s…
926 #define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive…
927 #define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a l…
928 #define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a h…
929 #define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a f…
930 #define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a r…
931 #define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any…
932 #define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any…
933 #define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */
934 #define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit…
935 #define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit…
936 /* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
937 #define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */
938 #define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */
939 #define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant…
940 #define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per …
941 #define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit…
942 #define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit…
943 #define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive…
944 #define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive…
945 #define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive…
946 #define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive…
947 #define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive…
948 #define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive…
949 #define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge …
950 /* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
951 /* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
952 #define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Valu…
953 #define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data E…
954 /* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
955 #define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */
956 #define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */
957 #define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmissi…
958 #define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer E…
959 #define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */
960 #define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */
961 #define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception …
962 #define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Fu…
963 #define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
964 #define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
965 #define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
966 #define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
967 /* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
968 /* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
969 /* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
990 /* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
991 #define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condit…
992 #define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Conditi…
993 #define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer…
994 #define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer…
995 #define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */
996 /* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
997 #define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Add…
998 #define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device …
999 #define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal d…
1000 #define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal d…
1001 #define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal…
1002 #define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Directi…
1003 #define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
1004 /* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
1005 #define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */
1006 #define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider …
1007 #define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */
1008 /* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
1009 #define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Comple…
1010 #define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding reg…
1011 #define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding re…
1012 #define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */
1013 #define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */
1014 #define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */
1015 /* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
1016 /* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
1017 /* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
1032 /* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
1033 #define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler …
1034 #define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */
1035 #define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */
1036 #define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */
1037 #define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
1038 #define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
1039 #define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Peri…
1040 /* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
1041 #define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle …
1042 /* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
1043 #define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */
1044 /* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
1045 #define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
1046 /* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
1047 #define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */
1068 /* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
1069 #define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
1070 #define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Pr…
1071 #define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */
1072 #define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
1073 #define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Pr…
1074 #define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */
1075 /* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
1076 #define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
1077 #define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
1078 #define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
1079 #define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1080 /* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
1081 /* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
1082 /* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
1083 /* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
1084 /* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
1085 /* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
1111 /* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
1112 #define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in th…
1113 #define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */
1114 #define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */
1115 /* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
1116 #define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */
1117 #define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */
1118 #define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */
1119 #define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the…
1120 #define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
1121 /* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
1122 #define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */
1123 #define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */
1124 /* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
1125 #define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
1126 #define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
1127 #define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
1128 #define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
1129 #define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
1130 #define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
1131 #define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
1132 #define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
1133 #define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt…
1134 #define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt …
1135 #define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
1136 /* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
1137 /* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
1138 /* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
1139 #define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Res…
1140 /* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
1141 /* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
1142 #define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0…
1143 #define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1…
1144 #define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2…
1145 #define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3…
1146 #define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4…
1147 #define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5…
1148 /* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
1149 #define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN …
1150 …ne AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 …
1151 #define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to t…
1152 #define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous erro…
1153 #define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet …
1154 #define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (use…
1155 #define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Ban…
1156 #define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Directi…
1157 #define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */
1158 #define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */
1159 #define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT …
1160 #define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */
1161 #define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */
1162 #define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */
1163 #define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */
1164 #define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */
1165 #define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */
1166 #define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable …
1167 #define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes …
1168 /* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
1169 #define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */
1170 #define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */
1190 /* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
1191 #define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock …
1192 #define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock …
1193 #define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigg…
1194 /* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode ------…
1195 #define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selectio…
1196 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected…
1197 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected…
1198 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected…
1199 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected…
1200 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected…
1201 #define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected…
1202 #define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected…
1203 #define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected…
1204 #define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */
1205 #define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal S…
1206 #define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is n…
1207 #define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed w…
1208 #define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed w…
1209 #define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed w…
1210 #define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock …
1211 #define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock …
1212 #define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock …
1213 #define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock …
1214 #define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigg…
1215 #define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
1216 #define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising e…
1217 #define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling …
1218 #define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edg…
1219 #define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event…
1220 #define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
1221 #define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising e…
1222 #define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling …
1223 #define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edg…
1224 #define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event…
1225 #define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selecte…
1226 #define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selecte…
1227 #define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selecte…
1228 #define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selecte…
1229 #define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB E…
1230 #define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event…
1231 #define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Sele…
1232 #define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode withou…
1233 #define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode wi…
1234 #define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with a…
1235 #define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode wi…
1236 #define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Tri…
1237 #define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
1238 #define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Eff…
1239 #define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
1240 #define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
1241 #define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear …
1242 #define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle…
1243 #define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Sel…
1244 #define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
1245 #define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising e…
1246 #define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling …
1247 #define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edg…
1248 #define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Eff…
1249 #define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
1250 #define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
1251 #define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear …
1252 #define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle…
1253 #define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Sel…
1254 #define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
1255 #define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising e…
1256 #define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling …
1257 #define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edg…
1258 #define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event…
1259 #define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
1260 #define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
1261 #define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear …
1262 #define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle…
1263 #define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigg…
1264 #define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
1265 #define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
1266 #define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear …
1267 #define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle…
1268 #define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Eff…
1269 #define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
1270 #define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
1271 #define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear …
1272 #define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle…
1273 #define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Eff…
1274 #define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
1275 #define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
1276 #define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear …
1277 #define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle…
1278 #define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event…
1279 #define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
1280 #define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
1281 #define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear …
1282 #define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle…
1283 #define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigg…
1284 #define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
1285 #define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
1286 #define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear …
1287 #define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle…
1288 /* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
1289 #define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overfl…
1290 #define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */
1291 #define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
1292 #define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */
1293 #define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */
1294 #define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */
1295 #define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */
1296 #define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigg…
1297 #define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling…
1298 #define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
1299 #define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
1300 /* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
1301 /* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
1302 /* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
1309 AT91S_TC TCB_TC0; /* TC Channel 0 */
1319 /* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
1320 #define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
1321 /* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
1322 …fine AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0…
1323 #define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC…
1324 #define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected…
1325 #define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC…
1326 #define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC…
1327 #define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal…
1328 #define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC…
1329 #define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected…
1330 #define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC…
1331 #define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC…
1332 #define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal…
1333 #define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC…
1334 #define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected…
1335 #define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC…
1336 #define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC…
1353 /* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
1354 #define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Time…
1355 #define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Prio…
1356 #define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Obje…
1357 #define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */
1358 #define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */
1359 #define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */
1360 #define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */
1361 #define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */
1362 #define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */
1363 /* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
1364 #define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementar…
1365 #define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier f…
1366 #define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier V…
1367 /* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
1368 /* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
1369 /* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
1370 #define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
1371 #define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Co…
1372 #define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmi…
1373 #define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort …
1374 #define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
1375 #define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignore…
1376 /* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
1377 /* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
1378 /* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
1379 #define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
1380 #define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
1401 AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */
1419 /* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
1420 #define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */
1421 #define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
1422 #define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen …
1423 #define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
1424 #define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end…
1425 #define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mod…
1426 #define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
1427 #define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */
1428 /* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
1429 #define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
1430 #define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
1431 #define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
1432 #define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
1433 #define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
1434 #define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
1435 #define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
1436 #define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
1437 #define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
1438 #define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
1439 #define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
1440 #define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
1441 #define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
1442 #define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
1443 #define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
1444 #define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
1445 #define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
1446 #define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
1447 #define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
1448 #define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
1449 #define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
1450 #define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
1451 #define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
1452 #define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
1453 #define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
1454 #define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
1455 #define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
1456 #define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
1457 #define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
1458 /* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
1459 /* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
1460 /* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
1461 #define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */
1462 #define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */
1463 #define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */
1464 /* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
1465 #define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */
1466 #define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */
1467 #define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */
1468 #define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width…
1469 #define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
1470 #define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */
1471 /* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
1472 #define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
1473 /* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
1474 /* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
1475 #define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */
1476 #define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
1477 /* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
1478 #define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */
1479 /* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
1521 AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */
1539 /* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
1540 #define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional…
1541 #define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */
1542 #define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */
1543 #define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */
1544 #define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port en…
1545 #define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics r…
1546 #define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statisti…
1547 #define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for s…
1548 #define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */
1549 #define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission…
1550 #define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt.…
1551 #define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause fra…
1552 #define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quan…
1553 /* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
1554 #define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */
1555 #define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */
1556 #define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
1557 #define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */
1558 #define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */
1559 #define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash eve…
1560 #define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enabl…
1561 #define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes…
1562 #define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address m…
1563 #define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
1564 #define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 …
1565 #define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16…
1566 #define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32…
1567 #define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64…
1568 #define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
1569 #define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
1570 #define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
1571 #define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from sta…
1572 #define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset fr…
1573 #define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset f…
1574 #define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset…
1575 #define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length fie…
1576 #define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FC…
1577 #define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
1578 #define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
1579 /* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
1580 #define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1581 #define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1582 #define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1583 /* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
1584 #define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1585 #define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1586 #define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1587 #define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */
1588 #define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted …
1589 #define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
1590 #define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
1591 /* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
1592 #define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1593 #define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1594 #define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1595 /* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
1596 #define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1597 #define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1598 #define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1599 #define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */
1600 #define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */
1601 #define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
1602 #define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
1603 #define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */
1604 #define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */
1605 #define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
1606 #define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
1607 #define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
1608 #define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
1609 /* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
1610 /* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
1611 /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
1612 /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
1613 #define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
1614 #define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */
1615 #define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */
1616 #define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */
1617 #define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */
1618 #define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */
1619 /* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
1620 #define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */
1621 /* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
1622 #define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
1623 #define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable…
1624 #define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable …
1625 #define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register…
1626 /* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
1627 #define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
1628 #define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
1646 AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
1667 /* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
1668 #define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset …
1669 #define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversio…
1670 /* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
1671 #define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable …
1672 #define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware trigge…
1673 #define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigge…
1674 #define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selecti…
1675 #define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL…
1676 #define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL…
1677 #define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL…
1678 #define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL…
1679 #define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL…
1680 #define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL…
1681 #define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL…
1682 #define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */
1683 #define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resoluti…
1684 #define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolutio…
1685 #define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
1686 #define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */
1687 #define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
1688 #define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate …
1689 #define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
1690 #define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold T…
1691 /* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
1692 #define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */
1693 #define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */
1694 #define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
1695 #define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */
1696 #define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */
1697 #define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */
1698 #define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */
1699 #define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */
1700 /* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
1701 /* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
1702 /* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
1703 #define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */
1704 #define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */
1705 #define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
1706 #define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */
1707 #define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */
1708 #define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */
1709 #define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */
1710 #define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */
1711 #define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */
1712 #define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */
1713 #define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */
1714 #define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */
1715 #define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */
1716 #define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */
1717 #define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */
1718 #define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */
1719 #define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */
1720 #define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */
1721 #define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
1722 #define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
1723 /* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
1724 #define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
1725 /* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
1726 /* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
1727 /* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
1728 /* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
1729 #define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */
1730 /* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
1731 /* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
1732 /* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
1733 /* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
1734 /* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
1735 /* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
1736 /* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
1769 /* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
1770 #define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing …
1771 #define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */
1772 #define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Gene…
1773 /* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
1774 #define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */
1775 #define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */
1776 #define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */
1777 #define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The S…
1778 #define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no acti…
1779 #define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datas…
1780 #define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */
1781 #define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic Cod…
1782 #define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block C…
1783 #define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedbac…
1784 #define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedbac…
1785 #define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. …
1786 #define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data M…
1787 #define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Da…
1788 #define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */
1789 #define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */
1790 #define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */
1791 #define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */
1792 #define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */
1793 #define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key…
1794 #define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Typ…
1795 #define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure typ…
1796 #define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure typ…
1797 #define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure typ…
1798 #define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure typ…
1799 #define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure typ…
1800 /* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
1801 #define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */
1802 #define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer En…
1803 #define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer E…
1804 #define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Fu…
1805 #define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer E…
1806 #define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Regist…
1807 /* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
1808 /* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
1809 /* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
1810 #define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspeci…
1811 #define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input d…
1812 #define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output …
1813 #define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode re…
1814 #define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output …
1815 #define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode re…
1816 #define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-o…
1853 /* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
1854 #define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */
1855 #define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */
1856 /* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
1857 #define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */
1858 #define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES…
1859 #define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */
1860 #define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */
1861 #define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The STA…
1862 #define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action…
1863 #define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datashe…
1864 #define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
1865 #define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeB…
1866 #define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Cha…
1867 #define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback …
1868 #define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback …
1869 #define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mod…
1870 #define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data…
1871 #define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
1872 #define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
1873 #define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
1874 #define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
1875 /* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
1876 #define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */
1877 #define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End …
1878 #define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End…
1879 #define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full…
1880 #define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Emp…
1881 #define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register…
1882 /* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
1883 /* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
1884 /* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
1885 #define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspe…
1886 #define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input…
1887 #define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Outpu…
1888 #define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode …
1889 #define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write…
1896 #define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
1897 #define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
1898 #define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
1899 #define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (P…
1900 #define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command …
1901 #define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
1902 #define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Regis…
1903 #define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command R…
1904 #define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register…
1905 #define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
1906 #define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Registe…
1907 #define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Regis…
1908 #define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command …
1909 #define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Reg…
1910 #define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Regi…
1911 #define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Reg…
1912 #define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command…
1913 #define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register …
1915 #define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Reg…
1916 #define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer…
1917 #define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointe…
1918 #define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Reg…
1919 #define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Regi…
1920 #define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Regi…
1921 #define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter…
1922 #define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control…
1923 #define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status …
1924 #define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counte…
1926 #define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Regist…
1927 #define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Regi…
1928 #define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Regist…
1929 #define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register …
1930 #define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
1931 #define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
1932 #define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register …
1933 #define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
1934 #define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
1935 #define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Regi…
1936 #define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Registe…
1937 #define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Registe…
1939 #define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr…
1940 #define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register…
1941 #define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Registe…
1942 #define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Registe…
1943 #define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Registe…
1944 #define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register…
1945 #define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register …
1946 #define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
1947 #define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Reg…
1948 #define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Reg…
1949 #define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Regi…
1950 #define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Regist…
1951 #define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Regis…
1952 #define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register …
1953 #define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Regi…
1954 #define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
1955 #define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Regi…
1956 #define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Regi…
1957 #define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register…
1958 #define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register …
1959 #define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
1960 #define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
1961 #define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Reg…
1962 #define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Regist…
1963 #define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Regi…
1964 #define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
1965 #define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Regi…
1966 #define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
1967 #define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
1969 #define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Reg…
1970 #define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Regi…
1971 #define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register …
1972 #define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register …
1973 #define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
1974 #define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register…
1975 #define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
1976 #define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Registe…
1977 #define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Regist…
1978 #define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Regi…
1979 #define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Registe…
1980 #define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Reg…
1981 #define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register…
1982 #define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Regist…
1983 #define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Regi…
1984 #define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
1985 #define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr…
1986 #define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Regi…
1987 #define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register …
1988 #define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register…
1989 #define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Registe…
1990 #define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Regis…
1991 #define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
1992 #define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Regi…
1993 #define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Regi…
1994 #define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
1995 #define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Reg…
1996 #define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
1997 #define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
1999 #define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register…
2000 #define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
2001 #define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Re…
2003 #define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Registe…
2004 #define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register …
2005 #define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
2006 #define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable R…
2007 #define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Regist…
2008 #define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
2009 #define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Regi…
2010 #define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable …
2011 #define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Regis…
2012 #define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status R…
2013 #define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Reg…
2014 #define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Regis…
2015 #define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
2016 #define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register…
2017 #define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
2019 #define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
2020 #define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
2021 #define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
2023 #define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Registe…
2024 #define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register …
2025 #define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register…
2026 #define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register…
2028 #define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Re…
2029 #define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status R…
2030 #define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Re…
2031 #define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Reg…
2033 #define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Registe…
2034 #define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register…
2035 #define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
2037 #define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode R…
2039 #define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
2040 #define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register …
2041 #define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register …
2042 #define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Re…
2043 #define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
2044 #define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
2046 #define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control…
2047 #define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Regi…
2048 #define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counte…
2049 #define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Reg…
2050 #define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointe…
2051 #define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Reg…
2052 #define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Regi…
2053 #define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer…
2054 #define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter…
2055 #define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status …
2057 #define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register …
2058 #define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Registe…
2059 #define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
2060 #define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
2061 #define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Regist…
2062 #define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
2063 #define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
2064 #define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
2065 #define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
2067 #define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control…
2068 #define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Reg…
2069 #define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Reg…
2070 #define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Regi…
2071 #define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status …
2072 #define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer…
2073 #define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Regi…
2074 #define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counte…
2075 #define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter…
2076 #define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointe…
2078 #define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Registe…
2079 #define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
2080 #define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Regist…
2081 #define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
2082 #define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
2083 #define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register …
2084 #define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
2085 #define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
2086 #define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
2088 #define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter …
2089 #define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control …
2090 #define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Regi…
2091 #define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status R…
2092 #define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer…
2093 #define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Regis…
2094 #define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer …
2095 #define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Regis…
2096 #define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter…
2097 #define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Regi…
2099 #define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
2100 #define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
2101 #define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Registe…
2102 #define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
2103 #define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Registe…
2104 #define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register…
2105 #define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Regis…
2106 #define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Re…
2107 #define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register…
2108 #define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Regis…
2109 #define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
2110 #define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
2111 #define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
2112 #define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
2114 #define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer…
2115 #define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer …
2116 #define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Regi…
2117 #define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control …
2118 #define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status R…
2119 #define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter…
2120 #define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Regi…
2121 #define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Regis…
2122 #define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Regis…
2123 #define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter …
2125 #define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Regis…
2126 #define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
2127 #define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
2128 #define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
2129 #define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
2130 #define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Re…
2131 #define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
2132 #define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Registe…
2133 #define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
2134 #define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register…
2135 #define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Registe…
2136 #define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Regis…
2137 #define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
2138 #define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register…
2140 #define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter…
2141 #define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Regis…
2142 #define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter …
2143 #define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Regi…
2144 #define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control …
2145 #define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Regi…
2146 #define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Regis…
2147 #define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer …
2148 #define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer…
2149 #define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status R…
2151 #define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register …
2152 #define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Regi…
2153 #define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Regis…
2154 #define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Registe…
2155 #define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register…
2156 #define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegiste…
2157 #define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register…
2158 #define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Reg…
2159 #define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
2160 #define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
2161 #define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Regis…
2162 #define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
2163 #define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
2164 #define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Regist…
2166 #define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register…
2167 #define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
2168 #define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
2169 #define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
2170 #define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register…
2171 #define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Registe…
2172 #define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register…
2173 #define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
2174 #define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator …
2175 #define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register …
2177 #define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Regis…
2178 #define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
2179 #define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Regis…
2180 #define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle R…
2181 #define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Regi…
2182 #define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Registe…
2184 #define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
2185 #define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Registe…
2186 #define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Regi…
2187 #define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Regis…
2188 #define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Regis…
2189 #define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle R…
2191 #define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
2192 #define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Regis…
2193 #define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Regis…
2194 #define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Regi…
2195 #define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle R…
2196 #define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Registe…
2198 #define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
2199 #define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Regis…
2200 #define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle R…
2201 #define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Registe…
2202 #define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Regis…
2203 #define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Regi…
2205 #define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable R…
2206 #define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
2207 #define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Re…
2208 #define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
2209 #define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Re…
2210 #define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
2211 #define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Regi…
2212 #define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
2213 #define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
2215 #define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
2216 #define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register…
2217 #define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
2218 #define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Regist…
2219 #define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register…
2220 #define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Stat…
2221 #define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Registe…
2222 #define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register …
2223 #define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
2224 #define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Regis…
2225 #define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
2226 #define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register…
2228 #define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
2229 #define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
2230 #define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
2231 #define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register …
2232 #define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Ca…
2233 #define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register…
2234 #define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
2235 #define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Registe…
2236 #define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
2237 #define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
2239 #define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
2240 #define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register …
2241 #define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register…
2242 #define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Registe…
2243 #define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
2244 #define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Ca…
2245 #define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
2246 #define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
2247 #define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
2248 #define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
2250 #define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Ca…
2251 #define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register …
2252 #define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
2253 #define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
2254 #define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
2255 #define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Registe…
2256 #define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
2257 #define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
2258 #define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register…
2259 #define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
2261 #define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
2262 #define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register…
2264 #define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Regi…
2265 #define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Ma…
2266 #define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Regis…
2267 #define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
2268 #define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Regist…
2269 #define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Reg…
2270 #define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Reg…
2271 #define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register…
2273 #define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Regi…
2274 #define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
2275 #define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register…
2276 #define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Regist…
2277 #define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Ma…
2278 #define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Reg…
2279 #define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Regis…
2280 #define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Reg…
2282 #define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Regis…
2283 #define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Reg…
2284 #define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
2285 #define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Regi…
2286 #define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register…
2287 #define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Ma…
2288 #define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Reg…
2289 #define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Regist…
2291 #define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Reg…
2292 #define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Ma…
2293 #define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
2294 #define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Regis…
2295 #define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register…
2296 #define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Regist…
2297 #define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Regi…
2298 #define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Reg…
2300 #define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
2301 #define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register…
2302 #define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Reg…
2303 #define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Reg…
2304 #define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Regist…
2305 #define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Regis…
2306 #define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Regi…
2307 #define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Ma…
2309 #define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Regist…
2310 #define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Regis…
2311 #define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Reg…
2312 #define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Reg…
2313 #define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
2314 #define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register…
2315 #define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Regi…
2316 #define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Ma…
2318 #define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Reg…
2319 #define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
2320 #define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Ma…
2321 #define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Regist…
2322 #define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Regi…
2323 #define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Regis…
2324 #define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Reg…
2325 #define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register…
2327 #define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Regis…
2328 #define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Reg…
2329 #define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Reg…
2330 #define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Regi…
2331 #define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
2332 #define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register…
2333 #define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Ma…
2334 #define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Regist…
2336 #define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register…
2337 #define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
2338 #define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register…
2339 #define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
2340 #define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
2341 #define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
2342 #define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Registe…
2343 #define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
2344 #define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
2345 #define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
2346 #define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
2347 #define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
2349 #define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Registe…
2350 #define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, …
2351 #define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Botto…
2352 #define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors …
2353 #define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register …
2354 #define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mis…
2355 #define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
2356 #define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Fr…
2357 #define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error …
2358 #define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register…
2359 #define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Botto…
2360 #define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register …
2361 #define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Botto…
2362 #define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register…
2363 #define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Regist…
2364 #define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Re…
2365 #define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Regi…
2366 #define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Registe…
2367 #define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0…
2368 #define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Po…
2369 #define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Regist…
2370 #define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
2371 #define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, …
2372 #define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors R…
2373 #define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register…
2374 #define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register…
2375 #define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Poi…
2376 #define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames…
2377 #define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Re…
2378 #define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] …
2379 #define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Registe…
2380 #define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Err…
2381 #define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum R…
2382 #define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register…
2383 #define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Re…
2384 #define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
2385 #define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register …
2386 #define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame R…
2387 #define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Re…
2388 #define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame…
2389 #define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register …
2390 #define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Botto…
2391 #define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Regis…
2392 #define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Registe…
2393 #define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, …
2394 #define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Regi…
2395 #define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, …
2396 #define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error …
2397 #define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register …
2399 #define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status R…
2400 #define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control …
2401 #define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer…
2402 #define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter…
2403 #define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer …
2404 #define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter …
2405 #define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Regis…
2406 #define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Regi…
2407 #define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Regi…
2408 #define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Regis…
2410 #define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register…
2411 #define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register…
2412 #define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register…
2413 #define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register…
2414 #define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Regis…
2415 #define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
2416 #define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register…
2417 #define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register…
2418 #define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data R…
2419 #define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Reg…
2420 #define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
2421 #define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register…
2422 #define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register…
2423 #define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Regi…
2424 #define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Regist…
2425 #define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Regist…
2426 #define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
2427 #define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Regist…
2429 #define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Regi…
2430 #define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control …
2431 #define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer …
2432 #define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter…
2433 #define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Regi…
2434 #define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Regis…
2435 #define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter …
2436 #define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer…
2437 #define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Regis…
2438 #define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status R…
2440 #define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x R…
2441 #define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
2442 #define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
2443 #define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
2444 #define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
2445 #define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
2446 #define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Registe…
2447 #define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
2448 #define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register…
2449 #define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
2450 #define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register…
2452 #define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter…
2453 #define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Reg…
2454 #define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Regi…
2455 #define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointe…
2456 #define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer…
2457 #define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Regi…
2458 #define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counte…
2459 #define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Reg…
2460 #define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status …
2461 #define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control…
2463 #define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
2464 #define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
2465 #define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Regist…
2466 #define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
2467 #define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x …
2468 #define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
2469 #define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register …
2470 #define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
2471 #define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
2472 #define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Registe…
2473 #define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Registe…
2474 #define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
2475 #define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
2480 #define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */
2481 #define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */
2483 #define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
2489 …AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
2491 #define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Sel…
2494 #define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Sel…
2497 #define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Sel…
2500 #define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
2502 #define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
2504 #define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
2508 #define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
2514 …AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
2539 #define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
2542 #define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */
2545 #define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
2553 #define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Sel…
2556 #define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Sel…
2559 #define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Sel…
2560 #define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */
2562 …T91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
2573 #define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external …
2576 #define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Sel…
2579 #define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Sel…
2587 #define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Sel…
2592 #define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */
2595 …e AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
2598 …T91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
2606 #define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurp…
2609 #define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurp…
2619 #define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */
2634 …ne AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
2647 #define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */
2651 #define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */
2653 #define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */
2659 #define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */
2683 #define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */
2684 #define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */
2685 #define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
2686 #define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */
2687 #define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */
2688 #define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */
2689 #define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */
2690 #define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */
2691 #define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */
2692 #define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */
2693 #define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */
2694 #define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */
2695 #define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */
2696 #define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */
2697 #define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
2698 #define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */
2699 #define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
2700 #define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */
2701 #define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */
2702 #define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */
2703 #define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */
2704 #define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */
2705 #define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */
2706 #define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */
2707 #define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */
2708 #define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
2709 #define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
2710 #define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
2711 #define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
2712 #define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */
2713 #define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */
2714 #define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */
2715 #define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */
2716 #define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */
2717 #define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */
2718 #define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */
2719 #define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */
2720 #define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */
2721 #define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */
2722 #define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */
2723 #define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
2724 #define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
2725 #define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
2726 #define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */
2727 #define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */
2728 #define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */
2729 #define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */
2730 #define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */
2731 #define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */
2732 #define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */
2733 #define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */
2738 #define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */
2739 #define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyt…
2740 #define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */
2741 #define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyt…