Lines Matching refs:AT91_REG
35 typedef volatile unsigned int AT91_REG; /* Hardware register definition */ typedef
42 AT91_REG SYSC_AIC_SMR[ 32 ]; /* Source Mode Register */
43 AT91_REG SYSC_AIC_SVR[ 32 ]; /* Source Vector Register */
44 AT91_REG SYSC_AIC_IVR; /* IRQ Vector Register */
45 AT91_REG SYSC_AIC_FVR; /* FIQ Vector Register */
46 AT91_REG SYSC_AIC_ISR; /* Interrupt Status Register */
47 AT91_REG SYSC_AIC_IPR; /* Interrupt Pending Register */
48 AT91_REG SYSC_AIC_IMR; /* Interrupt Mask Register */
49 AT91_REG SYSC_AIC_CISR; /* Core Interrupt Status Register */
50 AT91_REG Reserved0[ 2 ]; /* */
51 AT91_REG SYSC_AIC_IECR; /* Interrupt Enable Command Register */
52 AT91_REG SYSC_AIC_IDCR; /* Interrupt Disable Command Register */
53 AT91_REG SYSC_AIC_ICCR; /* Interrupt Clear Command Register */
54 AT91_REG SYSC_AIC_ISCR; /* Interrupt Set Command Register */
55 AT91_REG SYSC_AIC_EOICR; /* End of Interrupt Command Register */
56 AT91_REG SYSC_AIC_SPU; /* Spurious Vector Register */
57 AT91_REG SYSC_AIC_DCR; /* Debug Control Register (Protect) */
58 AT91_REG Reserved1[ 1 ]; /* */
59 AT91_REG SYSC_AIC_FFER; /* Fast Forcing Enable Register */
60 AT91_REG SYSC_AIC_FFDR; /* Fast Forcing Disable Register */
61 AT91_REG SYSC_AIC_FFSR; /* Fast Forcing Status Register */
62 AT91_REG Reserved2[ 45 ]; /* */
63 AT91_REG SYSC_DBGU_CR; /* Control Register */
64 AT91_REG SYSC_DBGU_MR; /* Mode Register */
65 AT91_REG SYSC_DBGU_IER; /* Interrupt Enable Register */
66 AT91_REG SYSC_DBGU_IDR; /* Interrupt Disable Register */
67 AT91_REG SYSC_DBGU_IMR; /* Interrupt Mask Register */
68 AT91_REG SYSC_DBGU_CSR; /* Channel Status Register */
69 AT91_REG SYSC_DBGU_RHR; /* Receiver Holding Register */
70 AT91_REG SYSC_DBGU_THR; /* Transmitter Holding Register */
71 AT91_REG SYSC_DBGU_BRGR; /* Baud Rate Generator Register */
72 AT91_REG Reserved3[ 7 ]; /* */
73 AT91_REG SYSC_DBGU_C1R; /* Chip ID1 Register */
74 AT91_REG SYSC_DBGU_C2R; /* Chip ID2 Register */
75 AT91_REG SYSC_DBGU_FNTR; /* Force NTRST Register */
76 AT91_REG Reserved4[ 45 ]; /* */
77 AT91_REG SYSC_DBGU_RPR; /* Receive Pointer Register */
78 AT91_REG SYSC_DBGU_RCR; /* Receive Counter Register */
79 AT91_REG SYSC_DBGU_TPR; /* Transmit Pointer Register */
80 AT91_REG SYSC_DBGU_TCR; /* Transmit Counter Register */
81 AT91_REG SYSC_DBGU_RNPR; /* Receive Next Pointer Register */
82 AT91_REG SYSC_DBGU_RNCR; /* Receive Next Counter Register */
83 AT91_REG SYSC_DBGU_TNPR; /* Transmit Next Pointer Register */
84 AT91_REG SYSC_DBGU_TNCR; /* Transmit Next Counter Register */
85 AT91_REG SYSC_DBGU_PTCR; /* PDC Transfer Control Register */
86 AT91_REG SYSC_DBGU_PTSR; /* PDC Transfer Status Register */
87 AT91_REG Reserved5[ 54 ]; /* */
88 AT91_REG SYSC_PIOA_PER; /* PIO Enable Register */
89 AT91_REG SYSC_PIOA_PDR; /* PIO Disable Register */
90 AT91_REG SYSC_PIOA_PSR; /* PIO Status Register */
91 AT91_REG Reserved6[ 1 ]; /* */
92 AT91_REG SYSC_PIOA_OER; /* Output Enable Register */
93 AT91_REG SYSC_PIOA_ODR; /* Output Disable Registerr */
94 AT91_REG SYSC_PIOA_OSR; /* Output Status Register */
95 AT91_REG Reserved7[ 1 ]; /* */
96 AT91_REG SYSC_PIOA_IFER; /* Input Filter Enable Register */
97 AT91_REG SYSC_PIOA_IFDR; /* Input Filter Disable Register */
98 AT91_REG SYSC_PIOA_IFSR; /* Input Filter Status Register */
99 AT91_REG Reserved8[ 1 ]; /* */
100 AT91_REG SYSC_PIOA_SODR; /* Set Output Data Register */
101 AT91_REG SYSC_PIOA_CODR; /* Clear Output Data Register */
102 AT91_REG SYSC_PIOA_ODSR; /* Output Data Status Register */
103 AT91_REG SYSC_PIOA_PDSR; /* Pin Data Status Register */
104 AT91_REG SYSC_PIOA_IER; /* Interrupt Enable Register */
105 AT91_REG SYSC_PIOA_IDR; /* Interrupt Disable Register */
106 AT91_REG SYSC_PIOA_IMR; /* Interrupt Mask Register */
107 AT91_REG SYSC_PIOA_ISR; /* Interrupt Status Register */
108 AT91_REG SYSC_PIOA_MDER; /* Multi-driver Enable Register */
109 AT91_REG SYSC_PIOA_MDDR; /* Multi-driver Disable Register */
110 AT91_REG SYSC_PIOA_MDSR; /* Multi-driver Status Register */
111 AT91_REG Reserved9[ 1 ]; /* */
112 AT91_REG SYSC_PIOA_PPUDR; /* Pull-up Disable Register */
113 AT91_REG SYSC_PIOA_PPUER; /* Pull-up Enable Register */
114 AT91_REG SYSC_PIOA_PPUSR; /* Pad Pull-up Status Register */
115 AT91_REG Reserved10[ 1 ]; /* */
116 AT91_REG SYSC_PIOA_ASR; /* Select A Register */
117 AT91_REG SYSC_PIOA_BSR; /* Select B Register */
118 AT91_REG SYSC_PIOA_ABSR; /* AB Select Status Register */
119 AT91_REG Reserved11[ 9 ]; /* */
120 AT91_REG SYSC_PIOA_OWER; /* Output Write Enable Register */
121 AT91_REG SYSC_PIOA_OWDR; /* Output Write Disable Register */
122 AT91_REG SYSC_PIOA_OWSR; /* Output Write Status Register */
123 AT91_REG Reserved12[ 469 ]; /* */
124 AT91_REG SYSC_PMC_SCER; /* System Clock Enable Register */
125 AT91_REG SYSC_PMC_SCDR; /* System Clock Disable Register */
126 AT91_REG SYSC_PMC_SCSR; /* System Clock Status Register */
127 AT91_REG Reserved13[ 1 ]; /* */
128 AT91_REG SYSC_PMC_PCER; /* Peripheral Clock Enable Register */
129 AT91_REG SYSC_PMC_PCDR; /* Peripheral Clock Disable Register */
130 AT91_REG SYSC_PMC_PCSR; /* Peripheral Clock Status Register */
131 AT91_REG Reserved14[ 1 ]; /* */
132 AT91_REG SYSC_PMC_MOR; /* Main Oscillator Register */
133 AT91_REG SYSC_PMC_MCFR; /* Main Clock Frequency Register */
134 AT91_REG Reserved15[ 1 ]; /* */
135 AT91_REG SYSC_PMC_PLLR; /* PLL Register */
136 AT91_REG SYSC_PMC_MCKR; /* Master Clock Register */
137 AT91_REG Reserved16[ 3 ]; /* */
138 AT91_REG SYSC_PMC_PCKR[ 8 ]; /* Programmable Clock Register */
139 AT91_REG SYSC_PMC_IER; /* Interrupt Enable Register */
140 AT91_REG SYSC_PMC_IDR; /* Interrupt Disable Register */
141 AT91_REG SYSC_PMC_SR; /* Status Register */
142 AT91_REG SYSC_PMC_IMR; /* Interrupt Mask Register */
143 AT91_REG Reserved17[ 36 ]; /* */
144 AT91_REG SYSC_RSTC_RCR; /* Reset Control Register */
145 AT91_REG SYSC_RSTC_RSR; /* Reset Status Register */
146 AT91_REG SYSC_RSTC_RMR; /* Reset Mode Register */
147 AT91_REG Reserved18[ 5 ]; /* */
148 AT91_REG SYSC_RTTC_RTMR; /* Real-time Mode Register */
149 AT91_REG SYSC_RTTC_RTAR; /* Real-time Alarm Register */
150 AT91_REG SYSC_RTTC_RTVR; /* Real-time Value Register */
151 AT91_REG SYSC_RTTC_RTSR; /* Real-time Status Register */
152 AT91_REG SYSC_PITC_PIMR; /* Period Interval Mode Register */
153 AT91_REG SYSC_PITC_PISR; /* Period Interval Status Register */
154 AT91_REG SYSC_PITC_PIVR; /* Period Interval Value Register */
155 AT91_REG SYSC_PITC_PIIR; /* Period Interval Image Register */
156 AT91_REG SYSC_WDTC_WDCR; /* Watchdog Control Register */
157 AT91_REG SYSC_WDTC_WDMR; /* Watchdog Mode Register */
158 AT91_REG SYSC_WDTC_WDSR; /* Watchdog Status Register */
159 AT91_REG Reserved19[ 5 ]; /* */
160 AT91_REG SYSC_SYSC_VRPM; /* Voltage Regulator Power Mode Register */
171 AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
172 AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
173 AT91_REG AIC_IVR; /* IRQ Vector Register */
174 AT91_REG AIC_FVR; /* FIQ Vector Register */
175 AT91_REG AIC_ISR; /* Interrupt Status Register */
176 AT91_REG AIC_IPR; /* Interrupt Pending Register */
177 AT91_REG AIC_IMR; /* Interrupt Mask Register */
178 AT91_REG AIC_CISR; /* Core Interrupt Status Register */
179 AT91_REG Reserved0[ 2 ]; /* */
180 AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
181 AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
182 AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
183 AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
184 AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
185 AT91_REG AIC_SPU; /* Spurious Vector Register */
186 AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
187 AT91_REG Reserved1[ 1 ]; /* */
188 AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
189 AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
190 AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
214 AT91_REG DBGU_CR; /* Control Register */
215 AT91_REG DBGU_MR; /* Mode Register */
216 AT91_REG DBGU_IER; /* Interrupt Enable Register */
217 AT91_REG DBGU_IDR; /* Interrupt Disable Register */
218 AT91_REG DBGU_IMR; /* Interrupt Mask Register */
219 AT91_REG DBGU_CSR; /* Channel Status Register */
220 AT91_REG DBGU_RHR; /* Receiver Holding Register */
221 AT91_REG DBGU_THR; /* Transmitter Holding Register */
222 AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
223 AT91_REG Reserved0[ 7 ]; /* */
224 AT91_REG DBGU_C1R; /* Chip ID1 Register */
225 AT91_REG DBGU_C2R; /* Chip ID2 Register */
226 AT91_REG DBGU_FNTR; /* Force NTRST Register */
227 AT91_REG Reserved1[ 45 ]; /* */
228 AT91_REG DBGU_RPR; /* Receive Pointer Register */
229 AT91_REG DBGU_RCR; /* Receive Counter Register */
230 AT91_REG DBGU_TPR; /* Transmit Pointer Register */
231 AT91_REG DBGU_TCR; /* Transmit Counter Register */
232 AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
233 AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
234 AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
235 AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
236 AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
237 AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
284 AT91_REG PDC_RPR; /* Receive Pointer Register */
285 AT91_REG PDC_RCR; /* Receive Counter Register */
286 AT91_REG PDC_TPR; /* Transmit Pointer Register */
287 AT91_REG PDC_TCR; /* Transmit Counter Register */
288 AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
289 AT91_REG PDC_RNCR; /* Receive Next Counter Register */
290 AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
291 AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
292 AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
293 AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
308 AT91_REG PIO_PER; /* PIO Enable Register */
309 AT91_REG PIO_PDR; /* PIO Disable Register */
310 AT91_REG PIO_PSR; /* PIO Status Register */
311 AT91_REG Reserved0[ 1 ]; /* */
312 AT91_REG PIO_OER; /* Output Enable Register */
313 AT91_REG PIO_ODR; /* Output Disable Registerr */
314 AT91_REG PIO_OSR; /* Output Status Register */
315 AT91_REG Reserved1[ 1 ]; /* */
316 AT91_REG PIO_IFER; /* Input Filter Enable Register */
317 AT91_REG PIO_IFDR; /* Input Filter Disable Register */
318 AT91_REG PIO_IFSR; /* Input Filter Status Register */
319 AT91_REG Reserved2[ 1 ]; /* */
320 AT91_REG PIO_SODR; /* Set Output Data Register */
321 AT91_REG PIO_CODR; /* Clear Output Data Register */
322 AT91_REG PIO_ODSR; /* Output Data Status Register */
323 AT91_REG PIO_PDSR; /* Pin Data Status Register */
324 AT91_REG PIO_IER; /* Interrupt Enable Register */
325 AT91_REG PIO_IDR; /* Interrupt Disable Register */
326 AT91_REG PIO_IMR; /* Interrupt Mask Register */
327 AT91_REG PIO_ISR; /* Interrupt Status Register */
328 AT91_REG PIO_MDER; /* Multi-driver Enable Register */
329 AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
330 AT91_REG PIO_MDSR; /* Multi-driver Status Register */
331 AT91_REG Reserved3[ 1 ]; /* */
332 AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
333 AT91_REG PIO_PPUER; /* Pull-up Enable Register */
334 AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
335 AT91_REG Reserved4[ 1 ]; /* */
336 AT91_REG PIO_ASR; /* Select A Register */
337 AT91_REG PIO_BSR; /* Select B Register */
338 AT91_REG PIO_ABSR; /* AB Select Status Register */
339 AT91_REG Reserved5[ 9 ]; /* */
340 AT91_REG PIO_OWER; /* Output Write Enable Register */
341 AT91_REG PIO_OWDR; /* Output Write Disable Register */
342 AT91_REG PIO_OWSR; /* Output Write Status Register */
351 AT91_REG CKGR_MOR; /* Main Oscillator Register */
352 AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
353 AT91_REG Reserved0[ 1 ]; /* */
354 AT91_REG CKGR_PLLR; /* PLL Register */
385 AT91_REG PMC_SCER; /* System Clock Enable Register */
386 AT91_REG PMC_SCDR; /* System Clock Disable Register */
387 AT91_REG PMC_SCSR; /* System Clock Status Register */
388 AT91_REG Reserved0[ 1 ]; /* */
389 AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
390 AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
391 AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
392 AT91_REG Reserved1[ 1 ]; /* */
393 AT91_REG PMC_MOR; /* Main Oscillator Register */
394 AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
395 AT91_REG Reserved2[ 1 ]; /* */
396 AT91_REG PMC_PLLR; /* PLL Register */
397 AT91_REG PMC_MCKR; /* Master Clock Register */
398 AT91_REG Reserved3[ 3 ]; /* */
399 AT91_REG PMC_PCKR[ 8 ]; /* Programmable Clock Register */
400 AT91_REG PMC_IER; /* Interrupt Enable Register */
401 AT91_REG PMC_IDR; /* Interrupt Disable Register */
402 AT91_REG PMC_SR; /* Status Register */
403 AT91_REG PMC_IMR; /* Interrupt Mask Register */
449 AT91_REG RSTC_RCR; /* Reset Control Register */
450 AT91_REG RSTC_RSR; /* Reset Status Register */
451 AT91_REG RSTC_RMR; /* Reset Mode Register */
482 AT91_REG RTTC_RTMR; /* Real-time Mode Register */
483 AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
484 AT91_REG RTTC_RTVR; /* Real-time Value Register */
485 AT91_REG RTTC_RTSR; /* Real-time Status Register */
506 AT91_REG PITC_PIMR; /* Period Interval Mode Register */
507 AT91_REG PITC_PISR; /* Period Interval Status Register */
508 AT91_REG PITC_PIVR; /* Period Interval Value Register */
509 AT91_REG PITC_PIIR; /* Period Interval Image Register */
528 AT91_REG WDTC_WDCR; /* Watchdog Control Register */
529 AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
530 AT91_REG WDTC_WDSR; /* Watchdog Status Register */
553 AT91_REG MC_RCR; /* MC Remap Control Register */
554 AT91_REG MC_ASR; /* MC Abort Status Register */
555 AT91_REG MC_AASR; /* MC Abort Address Status Register */
556 AT91_REG Reserved0[ 21 ]; /* */
557 AT91_REG MC_FMR; /* MC Flash Mode Register */
558 AT91_REG MC_FCR; /* MC Flash Command Register */
559 AT91_REG MC_FSR; /* MC Flash Status Register */
634 AT91_REG SPI_CR; /* Control Register */
635 AT91_REG SPI_MR; /* Mode Register */
636 AT91_REG SPI_RDR; /* Receive Data Register */
637 AT91_REG SPI_TDR; /* Transmit Data Register */
638 AT91_REG SPI_SR; /* Status Register */
639 AT91_REG SPI_IER; /* Interrupt Enable Register */
640 AT91_REG SPI_IDR; /* Interrupt Disable Register */
641 AT91_REG SPI_IMR; /* Interrupt Mask Register */
642 AT91_REG Reserved0[ 4 ]; /* */
643 AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */
644 AT91_REG Reserved1[ 48 ]; /* */
645 AT91_REG SPI_RPR; /* Receive Pointer Register */
646 AT91_REG SPI_RCR; /* Receive Counter Register */
647 AT91_REG SPI_TPR; /* Transmit Pointer Register */
648 AT91_REG SPI_TCR; /* Transmit Counter Register */
649 AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
650 AT91_REG SPI_RNCR; /* Receive Next Counter Register */
651 AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
652 AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
653 AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
654 AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
717 AT91_REG ADC_CR; /* ADC Control Register */
718 AT91_REG ADC_MR; /* ADC Mode Register */
719 AT91_REG Reserved0[ 2 ]; /* */
720 AT91_REG ADC_CHER; /* ADC Channel Enable Register */
721 AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
722 AT91_REG ADC_CHSR; /* ADC Channel Status Register */
723 AT91_REG ADC_SR; /* ADC Status Register */
724 AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
725 AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
726 AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
727 AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
728 AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
729 AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
730 AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
731 AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
732 AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
733 AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
734 AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
735 AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
736 AT91_REG Reserved1[ 44 ]; /* */
737 AT91_REG ADC_RPR; /* Receive Pointer Register */
738 AT91_REG ADC_RCR; /* Receive Counter Register */
739 AT91_REG ADC_TPR; /* Transmit Pointer Register */
740 AT91_REG ADC_TCR; /* Transmit Counter Register */
741 AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
742 AT91_REG ADC_RNCR; /* Receive Next Counter Register */
743 AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
744 AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
745 AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
746 AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
825 AT91_REG SSC_CR; /* Control Register */
826 AT91_REG SSC_CMR; /* Clock Mode Register */
827 AT91_REG Reserved0[ 2 ]; /* */
828 AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
829 AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
830 AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
831 AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
832 AT91_REG SSC_RHR; /* Receive Holding Register */
833 AT91_REG SSC_THR; /* Transmit Holding Register */
834 AT91_REG Reserved1[ 2 ]; /* */
835 AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
836 AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
837 AT91_REG SSC_RC0R; /* Receive Compare 0 Register */
838 AT91_REG SSC_RC1R; /* Receive Compare 1 Register */
839 AT91_REG SSC_SR; /* Status Register */
840 AT91_REG SSC_IER; /* Interrupt Enable Register */
841 AT91_REG SSC_IDR; /* Interrupt Disable Register */
842 AT91_REG SSC_IMR; /* Interrupt Mask Register */
843 AT91_REG Reserved2[ 44 ]; /* */
844 AT91_REG SSC_RPR; /* Receive Pointer Register */
845 AT91_REG SSC_RCR; /* Receive Counter Register */
846 AT91_REG SSC_TPR; /* Transmit Pointer Register */
847 AT91_REG SSC_TCR; /* Transmit Counter Register */
848 AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
849 AT91_REG SSC_RNCR; /* Receive Next Counter Register */
850 AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
851 AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
852 AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
853 AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
932 AT91_REG US_CR; /* Control Register */
933 AT91_REG US_MR; /* Mode Register */
934 AT91_REG US_IER; /* Interrupt Enable Register */
935 AT91_REG US_IDR; /* Interrupt Disable Register */
936 AT91_REG US_IMR; /* Interrupt Mask Register */
937 AT91_REG US_CSR; /* Channel Status Register */
938 AT91_REG US_RHR; /* Receiver Holding Register */
939 AT91_REG US_THR; /* Transmitter Holding Register */
940 AT91_REG US_BRGR; /* Baud Rate Generator Register */
941 AT91_REG US_RTOR; /* Receiver Time-out Register */
942 AT91_REG US_TTGR; /* Transmitter Time-guard Register */
943 AT91_REG Reserved0[ 5 ]; /* */
944 AT91_REG US_FIDI; /* FI_DI_Ratio Register */
945 AT91_REG US_NER; /* Nb Errors Register */
946 AT91_REG US_XXR; /* XON_XOFF Register */
947 AT91_REG US_IF; /* IRDA_FILTER Register */
948 AT91_REG Reserved1[ 44 ]; /* */
949 AT91_REG US_RPR; /* Receive Pointer Register */
950 AT91_REG US_RCR; /* Receive Counter Register */
951 AT91_REG US_TPR; /* Transmit Pointer Register */
952 AT91_REG US_TCR; /* Transmit Counter Register */
953 AT91_REG US_RNPR; /* Receive Next Pointer Register */
954 AT91_REG US_RNCR; /* Receive Next Counter Register */
955 AT91_REG US_TNPR; /* Transmit Next Pointer Register */
956 AT91_REG US_TNCR; /* Transmit Next Counter Register */
957 AT91_REG US_PTCR; /* PDC Transfer Control Register */
958 AT91_REG US_PTSR; /* PDC Transfer Status Register */
1029 AT91_REG TWI_CR; /* Control Register */
1030 AT91_REG TWI_MMR; /* Master Mode Register */
1031 AT91_REG TWI_SMR; /* Slave Mode Register */
1032 AT91_REG TWI_IADR; /* Internal Address Register */
1033 AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
1034 AT91_REG Reserved0[ 3 ]; /* */
1035 AT91_REG TWI_SR; /* Status Register */
1036 AT91_REG TWI_IER; /* Interrupt Enable Register */
1037 AT91_REG TWI_IDR; /* Interrupt Disable Register */
1038 AT91_REG TWI_IMR; /* Interrupt Mask Register */
1039 AT91_REG TWI_RHR; /* Receive Holding Register */
1040 AT91_REG TWI_THR; /* Transmit Holding Register */
1085 AT91_REG TC_CCR; /* Channel Control Register */
1086 AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */
1087 AT91_REG Reserved0[ 2 ]; /* */
1088 AT91_REG TC_CV; /* Counter Value */
1089 AT91_REG TC_RA; /* Register A */
1090 AT91_REG TC_RB; /* Register B */
1091 AT91_REG TC_RC; /* Register C */
1092 AT91_REG TC_SR; /* Status Register */
1093 AT91_REG TC_IER; /* Interrupt Enable Register */
1094 AT91_REG TC_IDR; /* Interrupt Disable Register */
1095 AT91_REG TC_IMR; /* Interrupt Mask Register */
1218 AT91_REG Reserved0[ 4 ]; /* */
1220 AT91_REG Reserved1[ 4 ]; /* */
1222 AT91_REG Reserved2[ 4 ]; /* */
1223 AT91_REG TCB_BCR; /* TC Block Control Register */
1224 AT91_REG TCB_BMR; /* TC Block Mode Register */
1251 AT91_REG PWMC_CMR; /* Channel Mode Register */
1252 AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */
1253 AT91_REG PWMC_CPRDR; /* Channel Period Register */
1254 AT91_REG PWMC_CCNTR; /* Channel Counter Register */
1255 AT91_REG PWMC_CUPDR; /* Channel Update Register */
1256 AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
1281 AT91_REG PWMC_MR; /* PWMC Mode Register */
1282 AT91_REG PWMC_ENA; /* PWMC Enable Register */
1283 AT91_REG PWMC_DIS; /* PWMC Disable Register */
1284 AT91_REG PWMC_SR; /* PWMC Status Register */
1285 AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */
1286 AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */
1287 AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */
1288 AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */
1289 AT91_REG Reserved0[ 55 ]; /* */
1290 AT91_REG PWMC_VR; /* PWMC Version Register */
1291 AT91_REG Reserved1[ 64 ]; /* */
1323 AT91_REG UDP_NUM; /* Frame Number Register */
1324 AT91_REG UDP_GLBSTATE; /* Global State Register */
1325 AT91_REG UDP_FADDR; /* Function Address Register */
1326 AT91_REG Reserved0[ 1 ]; /* */
1327 AT91_REG UDP_IER; /* Interrupt Enable Register */
1328 AT91_REG UDP_IDR; /* Interrupt Disable Register */
1329 AT91_REG UDP_IMR; /* Interrupt Mask Register */
1330 AT91_REG UDP_ISR; /* Interrupt Status Register */
1331 AT91_REG UDP_ICR; /* Interrupt Clear Register */
1332 AT91_REG Reserved1[ 1 ]; /* */
1333 AT91_REG UDP_RSTEP; /* Reset Endpoint Register */
1334 AT91_REG Reserved2[ 1 ]; /* */
1335 AT91_REG UDP_CSR[ 8 ]; /* Endpoint Control and Status Register */
1336 AT91_REG UDP_FDR[ 8 ]; /* Endpoint FIFO Data Register */
1404 #define AT91C_SYSC_SYSC_VRPM ( ( AT91_REG * ) 0xFFFFFD60 ) /* (SYSC) Voltage Regulator Power Mod…
1406 #define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Regi…
1407 #define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Reg…
1408 #define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
1409 #define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Regist…
1410 #define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Reg…
1411 #define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Prot…
1412 #define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register…
1413 #define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
1414 #define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
1415 #define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Registe…
1416 #define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
1417 #define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register…
1418 #define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
1419 #define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
1420 #define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
1421 #define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Re…
1422 #define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Regist…
1423 #define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
1425 #define AT91C_DBGU_C2R ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID2 Register */
1426 #define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Registe…
1427 #define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
1428 #define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register …
1429 #define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
1430 #define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
1431 #define AT91C_DBGU_C1R ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID1 Register */
1432 #define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Registe…
1433 #define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
1434 #define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
1435 #define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
1436 #define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
1438 #define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter R…
1439 #define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Re…
1440 #define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Re…
1441 #define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Reg…
1442 #define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Registe…
1443 #define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Regist…
1444 #define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Registe…
1445 #define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Regist…
1446 #define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Re…
1447 #define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer R…
1449 #define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
1450 #define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
1451 #define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Regist…
1452 #define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
1453 #define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
1454 #define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Registe…
1455 #define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Registe…
1456 #define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
1457 #define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
1458 #define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
1459 #define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
1460 #define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
1461 #define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Regist…
1462 #define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
1463 #define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
1464 #define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Regist…
1465 #define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
1466 #define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
1467 #define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pad Pull-up Status Register…
1468 #define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register…
1469 #define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
1470 #define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Registe…
1471 #define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Registe…
1472 #define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
1473 #define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register …
1474 #define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
1475 #define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register …
1476 #define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Registe…
1477 #define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Registe…
1479 #define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
1480 #define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Regis…
1481 #define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
1483 #define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register…
1484 #define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register…
1485 #define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
1486 #define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
1487 #define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Reg…
1488 #define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Registe…
1489 #define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
1490 #define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
1491 #define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
1492 #define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
1493 #define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Regi…
1494 #define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Regi…
1495 #define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
1496 #define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Regist…
1497 #define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register …
1499 #define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
1500 #define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
1501 #define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
1503 #define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
1504 #define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
1505 #define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
1506 #define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
1508 #define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Regis…
1509 #define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Regi…
1510 #define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Regis…
1511 #define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Regist…
1513 #define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
1514 #define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
1515 #define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
1517 #define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
1518 #define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
1519 #define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
1520 #define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
1521 #define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Regis…
1522 #define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
1524 #define AT91C_SPI_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI) PDC Transfer Control Reg…
1525 #define AT91C_SPI_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI) Transmit Next Pointer Re…
1526 #define AT91C_SPI_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI) Receive Next Pointer Reg…
1527 #define AT91C_SPI_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI) Transmit Pointer Registe…
1528 #define AT91C_SPI_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI) Receive Pointer Register…
1529 #define AT91C_SPI_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI) PDC Transfer Status Regi…
1530 #define AT91C_SPI_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI) Transmit Next Counter Re…
1531 #define AT91C_SPI_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI) Receive Next Counter Reg…
1532 #define AT91C_SPI_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI) Transmit Counter Registe…
1533 #define AT91C_SPI_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI) Receive Counter Register…
1535 #define AT91C_SPI_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI) Chip Select Register */
1536 #define AT91C_SPI_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI) Interrupt Disable Register */
1537 #define AT91C_SPI_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI) Status Register */
1538 #define AT91C_SPI_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI) Receive Data Register */
1539 #define AT91C_SPI_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI) Control Register */
1540 #define AT91C_SPI_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI) Interrupt Mask Register */
1541 #define AT91C_SPI_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI) Interrupt Enable Register */
1542 #define AT91C_SPI_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI) Transmit Data Register */
1543 #define AT91C_SPI_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI) Mode Register */
1545 #define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Reg…
1546 #define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Re…
1547 #define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Reg…
1548 #define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Registe…
1549 #define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register…
1550 #define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Regi…
1551 #define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Re…
1552 #define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Reg…
1553 #define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Registe…
1554 #define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register…
1556 #define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register …
1557 #define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 …
1558 #define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 …
1559 #define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 …
1560 #define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 …
1561 #define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 …
1562 #define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 …
1563 #define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 …
1564 #define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
1565 #define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 …
1566 #define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
1567 #define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register …
1568 #define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register …
1569 #define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Registe…
1570 #define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
1571 #define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register…
1572 #define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Regist…
1573 #define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Regi…
1575 #define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Reg…
1576 #define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Re…
1577 #define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Reg…
1578 #define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Registe…
1579 #define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register…
1580 #define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Regi…
1581 #define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Re…
1582 #define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Reg…
1583 #define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Registe…
1584 #define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register…
1586 #define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register …
1587 #define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
1588 #define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
1589 #define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
1590 #define AT91C_SSC_RC0R ( ( AT91_REG * ) 0xFFFD4038 ) /* (SSC) Receive Compare 0 Register */
1591 #define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Registe…
1592 #define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
1593 #define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register…
1594 #define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
1595 #define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
1596 #define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
1597 #define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
1598 #define AT91C_SSC_RC1R ( ( AT91_REG * ) 0xFFFD403C ) /* (SSC) Receive Compare 1 Register */
1599 #define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Regist…
1600 #define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
1601 #define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register…
1603 #define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Regi…
1604 #define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Re…
1605 #define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Reg…
1606 #define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Registe…
1607 #define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register…
1608 #define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Reg…
1609 #define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Re…
1610 #define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Reg…
1611 #define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Registe…
1612 #define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register…
1614 #define AT91C_US1_XXR ( ( AT91_REG * ) 0xFFFC4048 ) /* (US1) XON_XOFF Register */
1615 #define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
1616 #define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
1617 #define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
1618 #define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
1619 #define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
1620 #define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register…
1621 #define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
1622 #define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
1623 #define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
1624 #define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register…
1625 #define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Regis…
1626 #define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
1627 #define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
1628 #define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
1630 #define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Reg…
1631 #define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Re…
1632 #define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Reg…
1633 #define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Registe…
1634 #define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register…
1635 #define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Regi…
1636 #define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Re…
1637 #define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Reg…
1638 #define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Registe…
1639 #define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register…
1641 #define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Regis…
1642 #define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register…
1643 #define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
1644 #define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
1645 #define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
1646 #define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
1647 #define AT91C_US0_XXR ( ( AT91_REG * ) 0xFFFC0048 ) /* (US0) XON_XOFF Register */
1648 #define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
1649 #define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
1650 #define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
1651 #define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
1652 #define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
1653 #define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
1654 #define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
1655 #define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register…
1657 #define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
1658 #define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
1659 #define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
1660 #define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Reg…
1661 #define AT91C_TWI_SMR ( ( AT91_REG * ) 0xFFFB8008 ) /* (TWI) Slave Mode Register */
1662 #define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
1663 #define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
1664 #define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
1665 #define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
1666 #define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
1667 #define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
1669 #define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
1670 #define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
1671 #define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
1672 #define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
1673 #define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Captu…
1674 #define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
1675 #define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
1676 #define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
1677 #define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
1678 #define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
1680 #define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
1681 #define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
1682 #define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
1683 #define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
1684 #define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Captu…
1685 #define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
1686 #define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
1687 #define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
1688 #define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
1689 #define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
1691 #define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
1692 #define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
1693 #define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
1694 #define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
1695 #define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Captu…
1696 #define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
1697 #define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
1698 #define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
1699 #define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
1700 #define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
1702 #define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
1703 #define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
1705 #define AT91C_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register…
1706 #define AT91C_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register…
1707 #define AT91C_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
1708 #define AT91C_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
1709 #define AT91C_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Registe…
1710 #define AT91C_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Regi…
1712 #define AT91C_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register…
1713 #define AT91C_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register…
1714 #define AT91C_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
1715 #define AT91C_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
1716 #define AT91C_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Registe…
1717 #define AT91C_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Regi…
1719 #define AT91C_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register…
1720 #define AT91C_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register…
1721 #define AT91C_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
1722 #define AT91C_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
1723 #define AT91C_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Registe…
1724 #define AT91C_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Regi…
1726 #define AT91C_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register…
1727 #define AT91C_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register…
1728 #define AT91C_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
1729 #define AT91C_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
1730 #define AT91C_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Registe…
1731 #define AT91C_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Regi…
1733 #define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
1734 #define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Regis…
1735 #define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Regi…
1736 #define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
1737 #define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
1738 #define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Registe…
1739 #define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
1740 #define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
1741 #define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Regis…
1743 #define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
1744 #define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
1745 #define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
1746 #define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register …
1747 #define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status …
1748 #define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
1749 #define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
1750 #define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
1751 #define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
1752 #define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
1753 #define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */