Lines Matching full:for
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
44 * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
49 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
54 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
69 …ed. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIM…
114 …Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for …
128 add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
138 * for the function is as per the other ports:
145 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
207 addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
208 store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
211 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-x15. */
213 addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
216 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
222 addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
236 …load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the…
268 …L_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task…
270 store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
284 csrr t0, mcause /* For viewing in the debugger only. */
285 csrr t1, mepc /* For viewing in the debugger only */
286 csrr t2, mstatus /* For viewing in the debugger only */
291 csrr t0, mcause /* For viewing in the debugger only. */
292 csrr t1, mepc /* For viewing in the debugger only */
293 csrr t2, mstatus /* For viewing in the debugger only */