Lines Matching +full:- +full:j
5 * SPDX-License-Identifier: MIT
30 * The FreeRTOS kernel's RISC-V port is split between the the code that is
31 * common across all currently supported RISC-V chips (implementations of the
32 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
34 * + The code that is common to all RISC-V chips is implemented in
35 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
36 * portASM.S file because the same file is used no matter which RISC-V chip is
39 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
42 * RISC-V chip that both includes a standard CLINT and does not add to the
43 * base set of RISC-V registers. There are additional
44 * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
45 * that do not include a standard CLINT or do add to the base set of RISC-V
54 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
55 * that include a standard CLINT and do not add to the base set of RISC-V
65 …S_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
69 …LINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
75 …resent) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
93 .extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit c…
98 /*-----------------------------------------------------------*/
106 /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
107 li a4, -1
110 …sw a4, 0(a0) /* Low word no smaller than old value to start with - will be overwrit…
114 …ime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
124 /* Update the 64-bit mtimer compare match value. */
133 /*-----------------------------------------------------------*/
141 * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
144 * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
148 * x0 zero Hard-wired zero -
151 * x3 gp Global pointer -
152 * x4 tp Thread pointer -
153 * x5-7 t0-2 Temporaries Caller
156 * x10-11 a0-1 Function Arguments/return values Caller
157 * x12-17 a2-7 Function arguments Caller
158 * x18-27 s2-11 Saved registers Callee
159 * x28-31 t3-6 Temporaries Caller
161 * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
205 addi a0, a0, -portWORD_SIZE
207 addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
211 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-x15. */
213 addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
216 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
222 addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
224 …addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
225 j chip_specific_stack_frame /* Until no more chip specific registers. */
227 addi a0, a0, -portWORD_SIZE
230 /*-----------------------------------------------------------*/
238 …_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
273 … /* Set MIE bit so the first task starts with interrupts enabled - required as returns …
281 /*-----------------------------------------------------------*/
287 j .
288 /*-----------------------------------------------------------*/
294 j .
295 /*-----------------------------------------------------------*/
309 /*-----------------------------------------------------------*/
316 /*-----------------------------------------------------------*/
327 /*-----------------------------------------------------------*/
342 j handle_interrupt
348 j handle_exception
355 …slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 o…
363 j processed_source
369 j processed_source
376 j processed_source
380 j processed_source /* No other exceptions handled yet. */
384 /*-----------------------------------------------------------*/