Lines Matching full:0
52 MSR SPSEL, #0
55 STP X0, X1, [SP, #-0x10]!
56 STP X2, X3, [SP, #-0x10]!
57 STP X4, X5, [SP, #-0x10]!
58 STP X6, X7, [SP, #-0x10]!
59 STP X8, X9, [SP, #-0x10]!
60 STP X10, X11, [SP, #-0x10]!
61 STP X12, X13, [SP, #-0x10]!
62 STP X14, X15, [SP, #-0x10]!
63 STP X16, X17, [SP, #-0x10]!
64 STP X18, X19, [SP, #-0x10]!
65 STP X20, X21, [SP, #-0x10]!
66 STP X22, X23, [SP, #-0x10]!
67 STP X24, X25, [SP, #-0x10]!
68 STP X26, X27, [SP, #-0x10]!
69 STP X28, X29, [SP, #-0x10]!
70 STP X30, XZR, [SP, #-0x10]!
82 STP X2, X3, [SP, #-0x10]!
93 CMP X2, #0
95 STP Q0, Q1, [SP,#-0x20]!
96 STP Q2, Q3, [SP,#-0x20]!
97 STP Q4, Q5, [SP,#-0x20]!
98 STP Q6, Q7, [SP,#-0x20]!
99 STP Q8, Q9, [SP,#-0x20]!
100 STP Q10, Q11, [SP,#-0x20]!
101 STP Q12, Q13, [SP,#-0x20]!
102 STP Q14, Q15, [SP,#-0x20]!
103 STP Q16, Q17, [SP,#-0x20]!
104 STP Q18, Q19, [SP,#-0x20]!
105 STP Q20, Q21, [SP,#-0x20]!
106 STP Q22, Q23, [SP,#-0x20]!
107 STP Q24, Q25, [SP,#-0x20]!
108 STP Q26, Q27, [SP,#-0x20]!
109 STP Q28, Q29, [SP,#-0x20]!
110 STP Q30, Q31, [SP,#-0x20]!
114 STP X2, X3, [SP, #-0x10]!
131 MSR SPSEL, #0
139 LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
146 CMP X3, #0
162 CMP X2, #0
164 LDP Q30, Q31, [SP], #0x20
165 LDP Q28, Q29, [SP], #0x20
166 LDP Q26, Q27, [SP], #0x20
167 LDP Q24, Q25, [SP], #0x20
168 LDP Q22, Q23, [SP], #0x20
169 LDP Q20, Q21, [SP], #0x20
170 LDP Q18, Q19, [SP], #0x20
171 LDP Q16, Q17, [SP], #0x20
172 LDP Q14, Q15, [SP], #0x20
173 LDP Q12, Q13, [SP], #0x20
174 LDP Q10, Q11, [SP], #0x20
175 LDP Q8, Q9, [SP], #0x20
176 LDP Q6, Q7, [SP], #0x20
177 LDP Q4, Q5, [SP], #0x20
178 LDP Q2, Q3, [SP], #0x20
179 LDP Q0, Q1, [SP], #0x20
181 LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
195 LDP X30, XZR, [SP], #0x10
196 LDP X28, X29, [SP], #0x10
197 LDP X26, X27, [SP], #0x10
198 LDP X24, X25, [SP], #0x10
199 LDP X22, X23, [SP], #0x10
200 LDP X20, X21, [SP], #0x10
201 LDP X18, X19, [SP], #0x10
202 LDP X16, X17, [SP], #0x10
203 LDP X14, X15, [SP], #0x10
204 LDP X12, X13, [SP], #0x10
205 LDP X10, X11, [SP], #0x10
206 LDP X8, X9, [SP], #0x10
207 LDP X6, X7, [SP], #0x10
208 LDP X4, X5, [SP], #0x10
209 LDP X2, X3, [SP], #0x10
210 LDP X0, X1, [SP], #0x10
237 CMP X1, #0x15 /* 0x15 = SVC instruction. */
239 CMP X1, #0x17 /* 0x17 = SMC instruction. */
279 STP X0, X1, [SP, #-0x10]!
280 STP X2, X3, [SP, #-0x10]!
281 STP X4, X5, [SP, #-0x10]!
282 STP X6, X7, [SP, #-0x10]!
283 STP X8, X9, [SP, #-0x10]!
284 STP X10, X11, [SP, #-0x10]!
285 STP X12, X13, [SP, #-0x10]!
286 STP X14, X15, [SP, #-0x10]!
287 STP X16, X17, [SP, #-0x10]!
288 STP X18, X19, [SP, #-0x10]!
289 STP X29, X30, [SP, #-0x10]!
299 STP X2, X3, [SP, #-0x10]!
308 STP X1, X5, [SP, #-0x10]!
317 STP X0, X1, [SP, #-0x10]!
328 LDP X0, X1, [SP], #0x10
336 LDP X1, X5, [SP], #0x10
340 CMP X1, #0
346 CMP X1, #0
349 /* Reset ullPortYieldRequired to 0. */
350 MOV X2, #0
354 LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
365 LDP X29, X30, [SP], #0x10
366 LDP X18, X19, [SP], #0x10
367 LDP X16, X17, [SP], #0x10
368 LDP X14, X15, [SP], #0x10
369 LDP X12, X13, [SP], #0x10
370 LDP X10, X11, [SP], #0x10
371 LDP X8, X9, [SP], #0x10
372 LDP X6, X7, [SP], #0x10
373 LDP X4, X5, [SP], #0x10
374 LDP X2, X3, [SP], #0x10
375 LDP X0, X1, [SP], #0x10
384 LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
395 LDP X29, X30, [SP], #0x10
396 LDP X18, X19, [SP], #0x10
397 LDP X16, X17, [SP], #0x10
398 LDP X14, X15, [SP], #0x10
399 LDP X12, X13, [SP], #0x10
400 LDP X10, X11, [SP], #0x10
401 LDP X8, X9, [SP], #0x10
402 LDP X6, X7, [SP], #0x10
403 LDP X4, X5, [SP], #0x10
404 LDP X2, X3, [SP], #0x10
405 LDP X0, X1, [SP], #0x10