Lines Matching full:0
53 #define portNVIC_SYSTICK_CLK ( 0 )
57 …_UNPRIVILEGED_CRITICAL_SECTIONS is not defined. We recommend defining it to 0 in FreeRTOSConfig.h …
65 #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
66 #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
67 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
68 #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
69 #define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
70 #define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
74 #define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
75 #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
76 #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
77 #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
79 #define portMPU_ENABLE ( 0x01UL )
81 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
82 #define portMPU_REGION_VALID ( 0x10UL )
83 #define portMPU_REGION_ENABLE ( 0x01UL )
84 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
85 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
88 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
89 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
95 #define portINITIAL_XPSR ( 0x01000000 )
96 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
97 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
98 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
101 #define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) )
107 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
108 #define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
109 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
110 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
112 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
124 * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
125 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
136 #define portUINT32_MAX ( ~( ( uint32_t ) 0 ) )
182 * @return 1 if the processor is already privileged, 0 otherwise.
187 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
190 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
191 * Bit[0] = 0 --> The processor is running privileged
192 * Bit[0] = 1 --> The processor is running unprivileged.
219 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
231 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
233 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
240 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
242 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
252 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
265 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
267 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
282 static uint8_t ucMaxSysCallPriority = 0;
283 static uint32_t ulMaxPRIGROUPValue = 0;
300 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_PRIVILEGED; in pxPortInitialiseStack()
305 xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; in pxPortInitialiseStack()
308 xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ in pxPortInitialiseStack()
309 xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ in pxPortInitialiseStack()
310 xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ in pxPortInitialiseStack()
311 xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ in pxPortInitialiseStack()
312 xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ in pxPortInitialiseStack()
313 xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ in pxPortInitialiseStack()
314 xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ in pxPortInitialiseStack()
315 xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ in pxPortInitialiseStack()
320 xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ in pxPortInitialiseStack()
321 xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ in pxPortInitialiseStack()
322 xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ in pxPortInitialiseStack()
323 xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ in pxPortInitialiseStack()
324 xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ in pxPortInitialiseStack()
328 #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) in pxPortInitialiseStack()
338 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ in pxPortInitialiseStack()
344 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
362 "cmp r1, %0 \n" in vPortSVCHandler()
374 #else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
389 " b %0 \n" in vPortSVCHandler()
394 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
417 * argument (r0) is pulParam[ 0 ]. */ in vSVCHandler_C()
477 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
518 ( uxSystemCallImplementations[ ucSystemCallNumber ] != ( UBaseType_t ) 0 ) ) in vSystemCallEnter()
526 for( i = 0; i < ulStackFrameSize; i++ ) in vSystemCallEnter()
532 __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); in vSystemCallEnter()
576 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
579 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
583 __asm volatile ( "svc %0 \n" ::"i" ( portSVC_SYSTEM_CALL_EXIT ) : "memory" ); in vRequestSystemCallExit()
586 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
589 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
632 for( i = 0; i < ulStackFrameSize; i++ ) in vSystemCallExit()
638 __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); in vSystemCallExit()
671 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
692 …" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ in prvRestoreContextOfFirstTask()
703 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ in prvRestoreContextOfFirstTask()
705 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ in prvRestoreContextOfFirstTask()
708 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ in prvRestoreContextOfFirstTask()
709 …" ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. … in prvRestoreContextOfFirstTask()
710 …stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ in prvRestoreContextOfFirstTask()
712 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ in prvRestoreContextOfFirstTask()
714 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ in prvRestoreContextOfFirstTask()
730 " mov r0, #0 \n" in prvRestoreContextOfFirstTask()
755 * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct in xPortStartScheduler()
783 volatile uint32_t ulImplementedPrioBits = 0; in xPortStartScheduler()
807 * hardware. A priority of 0 is invalid because setting the BASEPRI in xPortStartScheduler()
808 * register to 0 unmasks all interrupts, and interrupts with priority 0 in xPortStartScheduler()
815 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); in xPortStartScheduler()
823 ucMaxPriorityValue <<= ( uint8_t ) 0x01; in xPortStartScheduler()
845 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); in xPortStartScheduler()
846 ulMaxPRIGROUPValue = 0; in xPortStartScheduler()
868 portNVIC_SHPR2_REG = 0; in xPortStartScheduler()
879 uxCriticalNesting = 0; in xPortStartScheduler()
881 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) in xPortStartScheduler()
889 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ in xPortStartScheduler()
897 " svc %0 \n" /* System call to start first task. */ in xPortStartScheduler()
903 return 0; in xPortStartScheduler()
953 if( uxCriticalNesting == 0 ) in vPortExitCritical()
968 if( uxCriticalNesting == 0 ) in vPortExitCritical()
977 if( uxCriticalNesting == 0 ) in vPortExitCritical()
1006 " mov r0, %0 \n" in xPortPendSVHandler()
1011 " mov r0, #0 \n" in xPortPendSVHandler()
1020 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ in xPortPendSVHandler()
1022 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ in xPortPendSVHandler()
1025 " ldr r0, =0xe000ed9c \n" /* Region Base Address register. */ in xPortPendSVHandler()
1026 …" ldmia r2!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. … in xPortPendSVHandler()
1027 …stmia r0, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ in xPortPendSVHandler()
1029 " ldr r0, =0xe000ed94 \n" /* MPU_CTRL register. */ in xPortPendSVHandler()
1031 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ in xPortPendSVHandler()
1087 portNVIC_SYSTICK_CTRL_REG = 0UL; in vPortSetupTimerInterrupt()
1088 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; in vPortSetupTimerInterrupt()
1191 …" movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that th… in xIsPrivileged()
1192 …" moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the… in xIsPrivileged()
1242 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = in vPortStoreTaskMPUSettings()
1247 xMPUSettings->xRegion[ 0 ].ulRegionAttribute = in vPortStoreTaskMPUSettings()
1254 … xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) __SRAM_segment_start__; in vPortStoreTaskMPUSettings()
1255 xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) __SRAM_segment_end__; in vPortStoreTaskMPUSettings()
1256 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | in vPortStoreTaskMPUSettings()
1263 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; in vPortStoreTaskMPUSettings()
1264 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; in vPortStoreTaskMPUSettings()
1265 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; in vPortStoreTaskMPUSettings()
1266 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; in vPortStoreTaskMPUSettings()
1275 if( ulStackDepth > 0 ) in vPortStoreTaskMPUSettings()
1278 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = in vPortStoreTaskMPUSettings()
1283 xMPUSettings->xRegion[ 0 ].ulRegionAttribute = in vPortStoreTaskMPUSettings()
1289 xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; in vPortStoreTaskMPUSettings()
1290 …xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfSt… in vPortStoreTaskMPUSettings()
1292 xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | in vPortStoreTaskMPUSettings()
1296 lIndex = 0; in vPortStoreTaskMPUSettings()
1300 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) in vPortStoreTaskMPUSettings()
1317 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; in vPortStoreTaskMPUSettings()
1334 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; in vPortStoreTaskMPUSettings()
1335 xMPUSettings->xRegionSettings[ ul ].ulRegionStartAddress = 0UL; in vPortStoreTaskMPUSettings()
1336 xMPUSettings->xRegionSettings[ ul ].ulRegionEndAddress = 0UL; in vPortStoreTaskMPUSettings()
1337 xMPUSettings->xRegionSettings[ ul ].ulRegionPermissions = 0UL; in vPortStoreTaskMPUSettings()
1366 for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) in xPortIsAuthorizedToAccessBuffer()
1395 __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); in vPortValidateInterruptPriority()
1438 * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the in vPortValidateInterruptPriority()
1448 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1464 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1467 #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
1483 #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
1486 #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
1517 …AccessControlList[ ulAccessControlListEntryIndex ] & ( 1U << ulAccessControlListEntryBit ) ) != 0 ) in xPortIsAuthorizedToAccessKernelObject()
1540 #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */