Lines Matching full:2
64 AT91_REG Reserved0[ 2 ]; /* */
228 AT91_REG Reserved0[ 2 ]; /* */
316 #define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
429 … ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
476 #define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Pre…
477 #define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
478 … AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
479 #define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided…
480 #define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided…
481 #define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided…
482 #define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided…
483 #define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided…
487 #define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Dis…
509 #define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Rese…
646 #define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
650 …0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations…
651 #define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Rea…
671 #define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock St…
679 #define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock St…
732 #define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
747 #define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
846 …nsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop…
847 #define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
857 #define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/E…
880 AT91_REG Reserved0[ 2 ]; /* */
887 AT91_REG Reserved1[ 2 ]; /* */
890 AT91_REG Reserved2[ 2 ]; /* */
919 #define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit…
920 #define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit…
921 #define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Recei…
922 #define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit…
957 #define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmissi…
993 #define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer…
1011 #define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding re…
1078 #define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
1105 AT91_REG Reserved3[ 2 ]; /* */
1118 #define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */
1127 #define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
1144 #define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2…
1151 #define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to t…
1179 AT91_REG Reserved0[ 2 ]; /* */
1193 #define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigg…
1291 #define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
1313 AT91S_TC TCB_TC2; /* TC Channel 2 */
1327 #define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal…
1328 #define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC…
1329 #define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected…
1330 #define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC…
1331 #define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC…
1332 …CB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
1403 AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */
1422 #define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen …
1431 #define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
1465 #define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */
1489 AT91_REG Reserved0[ 2 ]; /* */
1524 AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */
1525 AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */
1526 AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */
1528 AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */
1530 AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */
1542 #define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */
1582 #define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1586 #define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1594 #define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1598 #define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1637 AT91_REG Reserved0[ 2 ]; /* */
1648 AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
1694 #define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
1705 #define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
1731 /* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
1745 AT91_REG Reserved0[ 2 ]; /* */
1796 …AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
1803 #define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer E…
1825 AT91_REG Reserved0[ 2 ]; /* */
1830 AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
1831 AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
1832 AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
1833 AT91_REG Reserved1[ 2 ]; /* */
1834 AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
1835 AT91_REG Reserved2[ 2 ]; /* */
1836 AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
1837 AT91_REG Reserved3[ 2 ]; /* */
1838 AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */
1878 #define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End…
2350 …MAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
2371 …MAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
2390 #define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Botto…
2393 …MAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
2395 …MAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
2410 …ne AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
2463 #define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
2494 …AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
2498 #define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external …
2507 #define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */
2529 …AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
2540 …AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
2543 …T91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
2556 …AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
2566 …e AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
2570 …AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
2575 …ne AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
2579 …AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
2594 #define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */
2600 #define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */
2604 …T91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
2618 #define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurp…
2621 #define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurp…
2625 #define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */
2629 …T91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
2649 #define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */
2661 #define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */
2805 AT91C_US_RSTRX EQU( 0x1 << 2 );
2923 -( CKGR ) Divider output is PLL clock output divided by 2
2957 AT91C_PMC_PRES EQU( 0x7 << 2 );
2959 AT91C_PMC_PRES_CLK EQU( 0x0 << 2 );
2961 AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 );
2962 -( PMC ) Selected clock divided by 2
2963 AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 );
2965 AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 );
2967 AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 );
2969 AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 );
2971 AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 );
2977 AT91C_PMC_LOCK EQU( 0x1 << 2 );
2999 AT91C_RSTC_PERRST EQU( 0x1 << 2 );
3158 AT91C_MC_LOCKE EQU( 0x1 << 2 );
3169 for Read, 2
3173 -( MC ) 2 cycles
3223 -( MC ) Sector 2 Lock Status
3239 -( MC ) Sector 2 Lock Status
3288 AT91C_SPI_PCSDEC EQU( 0x1 << 2 );
3315 AT91C_SPI_MODF EQU( 0x1 << 2 );
3442 … -( USART ) Asynchronous( SYNC = 0 ) 2 stop bits Synchronous( SYNC = 1 ) 2 stop bits
3444 -( USART ) 2 stop bits
3462 AT91C_US_RXBRK EQU( 0x1 << 2 );
3513 AT91C_SSC_CKO EQU( 0x7 << 2 );
3515 AT91C_SSC_CKO_NONE EQU( 0x0 << 2 );
3517 AT91C_SSC_CKO_CONTINUOUS EQU( 0x1 << 2 );
3519 AT91C_SSC_CKO_DATA_TX EQU( 0x2 << 2 );
3585 AT91C_SSC_ENDTX EQU( 0x1 << 2 );
3617 AT91C_TWI_MSEN EQU( 0x1 << 2 );
3650 AT91C_TWI_TXRDY EQU( 0x1 << 2 );
3714 AT91C_PWMC_CHID2 EQU( 0x1 << 2 );
3715 -( PWMC ) Channel ID 2
3740 AT91C_UDP_ESR EQU( 0x1 << 2 );
3756 AT91C_UDP_EPINT2 EQU( 0x1 << 2 );
3757 -( UDP ) Endpoint 2 Interrupt
3785 AT91C_UDP_EP2 EQU( 0x1 << 2 );
3786 -( UDP ) Reset Endpoint 2
3798 AT91C_UDP_RXSETUP EQU( 0x1 << 2 );
3846 AT91C_TC_SWTRG EQU( 0x1 << 2 );
4040 AT91C_TC_CPAS EQU( 0x1 << 2 );
4079 AT91C_TCB_TC1XC1S EQU( 0x3 << 2 );
4081 AT91C_TCB_TC1XC1S_TCLK1 EQU( 0x0 << 2 );
4083 AT91C_TCB_TC1XC1S_NONE EQU( 0x1 << 2 );
4085 AT91C_TCB_TC1XC1S_TIOA0 EQU( 0x2 << 2 );
4087 AT91C_TCB_TC1XC1S_TIOA2 EQU( 0x3 << 2 );
4090 -( TCB ) External Clock Signal 2 Selection
4166 AT91C_CAN_ABM EQU( 0x1 << 2 );
4183 AT91C_CAN_MB2 EQU( 0x1 << 2 );
4184 -( CAN ) Mailbox 2 Flag
4248 -( CAN ) Phase 2 segment
4281 AT91C_EMAC_RE EQU( 0x1 << 2 );
4361 AT91C_EMAC_IDLE EQU( 0x1 << 2 );
4368 AT91C_EMAC_RLES EQU( 0x1 << 2 );
4383 AT91C_EMAC_OVR EQU( 0x1 << 2 );
4390 AT91C_EMAC_RXUBR EQU( 0x1 << 2 );
4500 AT91C_ADC_CH2 EQU( 0x1 << 2 );
4501 -( ADC ) Channel 2
4519 AT91C_ADC_EOC2 EQU( 0x1 << 2 );
4565 /* - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
4628 -( AES ) Countermeasure type 2 is enabled.
4640 AT91C_AES_ENDTX EQU( 0x1 << 2 );
4716 AT91C_TDES_ENDTX EQU( 0x1 << 2 );
5609 … -( EMAC ) Specific Address 4 Top, Last 2 bytes
5651 … -( EMAC ) Specific Address 2 Top, Last 2 bytes
5689 … -( EMAC ) Specific Address 2 Bottom, First 4 bytes
5695 … -( EMAC ) Specific Address 1 Top, Last 2 bytes
5699 … -( EMAC ) Specific Address 3 Top, Last 2 bytes
5727 -( ADC ) ADC Channel Data Register 2
5829 -( TDES ) Key 2 Word x Register
5887 -SPI 0 Peripheral Chip Select 2
5895 -Timer Counter 2 external clock input
5912 AT91C_PIO_PA2 EQU( 1 << 2 );
5957 -SPI 1 Peripheral Chip Select 2
5979 -SPI 1 Peripheral Chip Select 2
5985 -PMC Programmable Clock Output 2
6011 -SPI 0 Peripheral Chip Select 2
6031 -Ethernet MAC Transmit Data 2
6039 -SPI 1 Peripheral Chip Select 2
6049 -Ethernet MAC Receive Data 2
6057 -SPI 0 Peripheral Chip Select 2
6086 AT91C_PIO_PB2 EQU( 1 << 2 );
6099 -PWM Channel 2
6107 -PMC Programmable Clock Output 2
6135 … -Timer Counter 2 Multipurpose Timer I / O Pin A
6141 … -Timer Counter 2 Multipurpose Timer I / O Pin B
6149 -PWM Channel 2
6157 -PMC Programmable Clock Output 2
6192 AT91C_ID_PIOA EQU( 2 );
6217 -Timer Counter 2