Lines Matching +full:0 +full:m
10 Multiprocessing (AMP) support in 2017, FreeRTOS Version 11.0.0 is the
49 FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices.
58 + Make taskYIELD available to unprivileged tasks for ARMv8-M ports.
61 + Update the SysTick setup code for ARMv8-M ports to first configure the clock
63 versions older than 7.0.0, which causes an emulation error if SysTick is
67 ARMv7-M ports to the ARMv8-M ports. We thank @jefftenney for their
98 introduced in version 10.6.0:
121 Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023
214 + Add assertions to ARMv8-M ports to detect when FreeRTOS APIs are called from
221 + Update interrupt priority asserts for Cortex-M ports so that these do not fire
223 + Update ARMv7-M ports to ensure that kernel interrupts run at the lowest priority.
224 configKERNEL_INTERRUPT_PRIORITY is now obsolete for ARMv7-M ports and brings
225 these ports inline with the newer ARMv8-M ports. Contributed by @chrisnc.
237 + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
245 + ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task
254 + ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
264 + ARMv7-M MPU ports: It was possible to configure overlapping memory
298 the option is set to 0, then the default callbacks as defined by
300 backwards compatibility, configUSE_SB_COMPLETED_CALLBACK defaults to 0. The
320 However, when configUSE_MINI_LIST_ITEM == 0, MiniLitItem_t and ListItem_t
382 + ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the
388 0 to disable critical sections from unprivileged tasks.
404 configIDLE_SHOULD_YIELD is set to 0.
405 + ARMv8-M secure-side port: Tasks that call secure functions from the
406 non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two
408 versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures
447 + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from
475 + Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked
482 + Update WolfSSL to 4.5.0 and add the FIPS ready demo.
510 + Kernel ports that support memory protection units (MPUs): The ARMv7-M and
511 ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M
515 the Flash memory. The ARMv8-M MPU ports now support tickless idle mode.
561 previously it was always assumed FreeRTOS was running on HART 0.
567 + Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to
568 match that of the ARMv8-M ports whereby privilege escalations can only
606 + Introduced the portDONT_DISCARD macro to the ARMv8-M ports to try and
622 + Included pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports
684 simply call exit( 0 ).
757 + Cortex-M ports push additional register prior to calling
762 Cortex-M devices.
819 value of than than 0 when the system boots. This can be useful for
822 + Ensure the Cortex-M SysTick count is cleared to zero before starting the
824 + Add configASSERT() into ARM Cortex-M ports to check the number of priority
943 configUSE_PREEMPTION is 0.
1089 + Exclude the whole of croutine.c if configUSE_CO_ROUTINES is set to 0.
1148 + configASSERT()s in all Cortex-M ports used to test the lowest 5 bits of
1152 + Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0
1162 + Update FreeRTOS+Trace recorder library to version 2.7.0.
1210 + configUSE_PORT_OPTIMISED_TASK_SELECTION now defaults to 1 instead of 0.
1223 + Fix a bug in the Tasking compiler's Cortex-M port that resulted in an
1324 configUSE_PREEMPTION is set to 0). It is important to note that the
1326 description only applies when configUSE_PREEMPTION is set to 0:
1328 WHEN configUSE_PREEMPTION IS SET TO 0 (which is in a small minority of
1338 set to 0, so the normal pre-emptive scheduler is being used, then task B
1386 + Improved behaviour and robustness of the default Cortex-M tickless idle
1424 V7.5.2 makes the new Cortex-M vPortCheckInterruptPriority() function
1428 tickless implementation need update from version 7.5.0.
1512 the yield macros of Cortex-M and Cortex-R port layers. For efficiency
1513 the Cortex-M port layer "yield" and "yield" from ISR are now implemented
1583 macros in the Cortex-M ports. The save macro now returns the previous
1626 + Add #error macros into the Keil and IAR Cortex-M ports to ensure they
1628 to 0.
1631 parameter must not be set to 0.
1633 (defaulted to 0).
1879 different semantics required when using the latest (V1.0.2.0) version of
1954 + Added a "cpsie i" instruction before the "svc 0" instruction used to start
1956 interrupts are globally enabled prior to the "svc 0" instruction being
2011 + Changed all GCC ARM 7 ports to use 0 as the SWI instruction parameter.
2012 Previously the parameter was blank and therefore only an implicit 0 but
2109 + Set configUSE_16_BIT_TICKS to 0 in the PPC405 demo projects.
2416 + Updated the PIC24 and dsPIC demos to build with V3.0 of the PIC30 GCC
2659 + Both PIC18 ports now initialise the TBLPTRU to 0 as this is the value
2975 portSTACK_GROWTH < 0.
3010 to 1 TickType_t is defined as an unsigned short. If set to 0
3062 0x18 to 0x08 - where it should have always been. The incorrect address