Lines Matching refs:AT91_REG
49 typedef volatile unsigned int AT91_REG;// Hardware register definition typedef
55 AT91_REG AIC_SMR[32]; // Source Mode Register
56 AT91_REG AIC_SVR[32]; // Source Vector Register
57 AT91_REG AIC_IVR; // IRQ Vector Register
58 AT91_REG AIC_FVR; // FIQ Vector Register
59 AT91_REG AIC_ISR; // Interrupt Status Register
60 AT91_REG AIC_IPR; // Interrupt Pending Register
61 AT91_REG AIC_IMR; // Interrupt Mask Register
62 AT91_REG AIC_CISR; // Core Interrupt Status Register
63 AT91_REG Reserved0[2]; //
64 AT91_REG AIC_IECR; // Interrupt Enable Command Register
65 AT91_REG AIC_IDCR; // Interrupt Disable Command Register
66 AT91_REG AIC_ICCR; // Interrupt Clear Command Register
67 AT91_REG AIC_ISCR; // Interrupt Set Command Register
68 AT91_REG AIC_EOICR; // End of Interrupt Command Register
69 AT91_REG AIC_SPU; // Spurious Vector Register
70 AT91_REG AIC_DCR; // Debug Control Register (Protect)
71 AT91_REG Reserved1[1]; //
72 AT91_REG AIC_FFER; // Fast Forcing Enable Register
73 AT91_REG AIC_FFDR; // Fast Forcing Disable Register
74 AT91_REG AIC_FFSR; // Fast Forcing Status Register
75 AT91_REG Reserved2[45]; //
76 AT91_REG DBGU_CR; // Control Register
77 AT91_REG DBGU_MR; // Mode Register
78 AT91_REG DBGU_IER; // Interrupt Enable Register
79 AT91_REG DBGU_IDR; // Interrupt Disable Register
80 AT91_REG DBGU_IMR; // Interrupt Mask Register
81 AT91_REG DBGU_CSR; // Channel Status Register
82 AT91_REG DBGU_RHR; // Receiver Holding Register
83 AT91_REG DBGU_THR; // Transmitter Holding Register
84 AT91_REG DBGU_BRGR; // Baud Rate Generator Register
85 AT91_REG Reserved3[7]; //
86 AT91_REG DBGU_CIDR; // Chip ID Register
87 AT91_REG DBGU_EXID; // Chip ID Extension Register
88 AT91_REG DBGU_FNTR; // Force NTRST Register
89 AT91_REG Reserved4[45]; //
90 AT91_REG DBGU_RPR; // Receive Pointer Register
91 AT91_REG DBGU_RCR; // Receive Counter Register
92 AT91_REG DBGU_TPR; // Transmit Pointer Register
93 AT91_REG DBGU_TCR; // Transmit Counter Register
94 AT91_REG DBGU_RNPR; // Receive Next Pointer Register
95 AT91_REG DBGU_RNCR; // Receive Next Counter Register
96 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
97 AT91_REG DBGU_TNCR; // Transmit Next Counter Register
98 AT91_REG DBGU_PTCR; // PDC Transfer Control Register
99 AT91_REG DBGU_PTSR; // PDC Transfer Status Register
100 AT91_REG Reserved5[54]; //
101 AT91_REG PIOA_PER; // PIO Enable Register
102 AT91_REG PIOA_PDR; // PIO Disable Register
103 AT91_REG PIOA_PSR; // PIO Status Register
104 AT91_REG Reserved6[1]; //
105 AT91_REG PIOA_OER; // Output Enable Register
106 AT91_REG PIOA_ODR; // Output Disable Registerr
107 AT91_REG PIOA_OSR; // Output Status Register
108 AT91_REG Reserved7[1]; //
109 AT91_REG PIOA_IFER; // Input Filter Enable Register
110 AT91_REG PIOA_IFDR; // Input Filter Disable Register
111 AT91_REG PIOA_IFSR; // Input Filter Status Register
112 AT91_REG Reserved8[1]; //
113 AT91_REG PIOA_SODR; // Set Output Data Register
114 AT91_REG PIOA_CODR; // Clear Output Data Register
115 AT91_REG PIOA_ODSR; // Output Data Status Register
116 AT91_REG PIOA_PDSR; // Pin Data Status Register
117 AT91_REG PIOA_IER; // Interrupt Enable Register
118 AT91_REG PIOA_IDR; // Interrupt Disable Register
119 AT91_REG PIOA_IMR; // Interrupt Mask Register
120 AT91_REG PIOA_ISR; // Interrupt Status Register
121 AT91_REG PIOA_MDER; // Multi-driver Enable Register
122 AT91_REG PIOA_MDDR; // Multi-driver Disable Register
123 AT91_REG PIOA_MDSR; // Multi-driver Status Register
124 AT91_REG Reserved9[1]; //
125 AT91_REG PIOA_PPUDR; // Pull-up Disable Register
126 AT91_REG PIOA_PPUER; // Pull-up Enable Register
127 AT91_REG PIOA_PPUSR; // Pull-up Status Register
128 AT91_REG Reserved10[1]; //
129 AT91_REG PIOA_ASR; // Select A Register
130 AT91_REG PIOA_BSR; // Select B Register
131 AT91_REG PIOA_ABSR; // AB Select Status Register
132 AT91_REG Reserved11[9]; //
133 AT91_REG PIOA_OWER; // Output Write Enable Register
134 AT91_REG PIOA_OWDR; // Output Write Disable Register
135 AT91_REG PIOA_OWSR; // Output Write Status Register
136 AT91_REG Reserved12[85]; //
137 AT91_REG PIOB_PER; // PIO Enable Register
138 AT91_REG PIOB_PDR; // PIO Disable Register
139 AT91_REG PIOB_PSR; // PIO Status Register
140 AT91_REG Reserved13[1]; //
141 AT91_REG PIOB_OER; // Output Enable Register
142 AT91_REG PIOB_ODR; // Output Disable Registerr
143 AT91_REG PIOB_OSR; // Output Status Register
144 AT91_REG Reserved14[1]; //
145 AT91_REG PIOB_IFER; // Input Filter Enable Register
146 AT91_REG PIOB_IFDR; // Input Filter Disable Register
147 AT91_REG PIOB_IFSR; // Input Filter Status Register
148 AT91_REG Reserved15[1]; //
149 AT91_REG PIOB_SODR; // Set Output Data Register
150 AT91_REG PIOB_CODR; // Clear Output Data Register
151 AT91_REG PIOB_ODSR; // Output Data Status Register
152 AT91_REG PIOB_PDSR; // Pin Data Status Register
153 AT91_REG PIOB_IER; // Interrupt Enable Register
154 AT91_REG PIOB_IDR; // Interrupt Disable Register
155 AT91_REG PIOB_IMR; // Interrupt Mask Register
156 AT91_REG PIOB_ISR; // Interrupt Status Register
157 AT91_REG PIOB_MDER; // Multi-driver Enable Register
158 AT91_REG PIOB_MDDR; // Multi-driver Disable Register
159 AT91_REG PIOB_MDSR; // Multi-driver Status Register
160 AT91_REG Reserved16[1]; //
161 AT91_REG PIOB_PPUDR; // Pull-up Disable Register
162 AT91_REG PIOB_PPUER; // Pull-up Enable Register
163 AT91_REG PIOB_PPUSR; // Pull-up Status Register
164 AT91_REG Reserved17[1]; //
165 AT91_REG PIOB_ASR; // Select A Register
166 AT91_REG PIOB_BSR; // Select B Register
167 AT91_REG PIOB_ABSR; // AB Select Status Register
168 AT91_REG Reserved18[9]; //
169 AT91_REG PIOB_OWER; // Output Write Enable Register
170 AT91_REG PIOB_OWDR; // Output Write Disable Register
171 AT91_REG PIOB_OWSR; // Output Write Status Register
172 AT91_REG Reserved19[341]; //
173 AT91_REG PMC_SCER; // System Clock Enable Register
174 AT91_REG PMC_SCDR; // System Clock Disable Register
175 AT91_REG PMC_SCSR; // System Clock Status Register
176 AT91_REG Reserved20[1]; //
177 AT91_REG PMC_PCER; // Peripheral Clock Enable Register
178 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
179 AT91_REG PMC_PCSR; // Peripheral Clock Status Register
180 AT91_REG Reserved21[1]; //
181 AT91_REG PMC_MOR; // Main Oscillator Register
182 AT91_REG PMC_MCFR; // Main Clock Frequency Register
183 AT91_REG Reserved22[1]; //
184 AT91_REG PMC_PLLR; // PLL Register
185 AT91_REG PMC_MCKR; // Master Clock Register
186 AT91_REG Reserved23[3]; //
187 AT91_REG PMC_PCKR[4]; // Programmable Clock Register
188 AT91_REG Reserved24[4]; //
189 AT91_REG PMC_IER; // Interrupt Enable Register
190 AT91_REG PMC_IDR; // Interrupt Disable Register
191 AT91_REG PMC_SR; // Status Register
192 AT91_REG PMC_IMR; // Interrupt Mask Register
193 AT91_REG Reserved25[36]; //
194 AT91_REG RSTC_RCR; // Reset Control Register
195 AT91_REG RSTC_RSR; // Reset Status Register
196 AT91_REG RSTC_RMR; // Reset Mode Register
197 AT91_REG Reserved26[5]; //
198 AT91_REG RTTC_RTMR; // Real-time Mode Register
199 AT91_REG RTTC_RTAR; // Real-time Alarm Register
200 AT91_REG RTTC_RTVR; // Real-time Value Register
201 AT91_REG RTTC_RTSR; // Real-time Status Register
202 AT91_REG PITC_PIMR; // Period Interval Mode Register
203 AT91_REG PITC_PISR; // Period Interval Status Register
204 AT91_REG PITC_PIVR; // Period Interval Value Register
205 AT91_REG PITC_PIIR; // Period Interval Image Register
206 AT91_REG WDTC_WDCR; // Watchdog Control Register
207 AT91_REG WDTC_WDMR; // Watchdog Mode Register
208 AT91_REG WDTC_WDSR; // Watchdog Status Register
209 AT91_REG Reserved27[5]; //
210 AT91_REG VREG_MR; // Voltage Regulator Mode Register
218 AT91_REG AIC_SMR[32]; // Source Mode Register
219 AT91_REG AIC_SVR[32]; // Source Vector Register
220 AT91_REG AIC_IVR; // IRQ Vector Register
221 AT91_REG AIC_FVR; // FIQ Vector Register
222 AT91_REG AIC_ISR; // Interrupt Status Register
223 AT91_REG AIC_IPR; // Interrupt Pending Register
224 AT91_REG AIC_IMR; // Interrupt Mask Register
225 AT91_REG AIC_CISR; // Core Interrupt Status Register
226 AT91_REG Reserved0[2]; //
227 AT91_REG AIC_IECR; // Interrupt Enable Command Register
228 AT91_REG AIC_IDCR; // Interrupt Disable Command Register
229 AT91_REG AIC_ICCR; // Interrupt Clear Command Register
230 AT91_REG AIC_ISCR; // Interrupt Set Command Register
231 AT91_REG AIC_EOICR; // End of Interrupt Command Register
232 AT91_REG AIC_SPU; // Spurious Vector Register
233 AT91_REG AIC_DCR; // Debug Control Register (Protect)
234 AT91_REG Reserved1[1]; //
235 AT91_REG AIC_FFER; // Fast Forcing Enable Register
236 AT91_REG AIC_FFDR; // Fast Forcing Disable Register
237 AT91_REG AIC_FFSR; // Fast Forcing Status Register
262 AT91_REG PDC_RPR; // Receive Pointer Register
263 AT91_REG PDC_RCR; // Receive Counter Register
264 AT91_REG PDC_TPR; // Transmit Pointer Register
265 AT91_REG PDC_TCR; // Transmit Counter Register
266 AT91_REG PDC_RNPR; // Receive Next Pointer Register
267 AT91_REG PDC_RNCR; // Receive Next Counter Register
268 AT91_REG PDC_TNPR; // Transmit Next Pointer Register
269 AT91_REG PDC_TNCR; // Transmit Next Counter Register
270 AT91_REG PDC_PTCR; // PDC Transfer Control Register
271 AT91_REG PDC_PTSR; // PDC Transfer Status Register
285 AT91_REG DBGU_CR; // Control Register
286 AT91_REG DBGU_MR; // Mode Register
287 AT91_REG DBGU_IER; // Interrupt Enable Register
288 AT91_REG DBGU_IDR; // Interrupt Disable Register
289 AT91_REG DBGU_IMR; // Interrupt Mask Register
290 AT91_REG DBGU_CSR; // Channel Status Register
291 AT91_REG DBGU_RHR; // Receiver Holding Register
292 AT91_REG DBGU_THR; // Transmitter Holding Register
293 AT91_REG DBGU_BRGR; // Baud Rate Generator Register
294 AT91_REG Reserved0[7]; //
295 AT91_REG DBGU_CIDR; // Chip ID Register
296 AT91_REG DBGU_EXID; // Chip ID Extension Register
297 AT91_REG DBGU_FNTR; // Force NTRST Register
298 AT91_REG Reserved1[45]; //
299 AT91_REG DBGU_RPR; // Receive Pointer Register
300 AT91_REG DBGU_RCR; // Receive Counter Register
301 AT91_REG DBGU_TPR; // Transmit Pointer Register
302 AT91_REG DBGU_TCR; // Transmit Counter Register
303 AT91_REG DBGU_RNPR; // Receive Next Pointer Register
304 AT91_REG DBGU_RNCR; // Receive Next Counter Register
305 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
306 AT91_REG DBGU_TNCR; // Transmit Next Counter Register
307 AT91_REG DBGU_PTCR; // PDC Transfer Control Register
308 AT91_REG DBGU_PTSR; // PDC Transfer Status Register
355 AT91_REG PIO_PER; // PIO Enable Register
356 AT91_REG PIO_PDR; // PIO Disable Register
357 AT91_REG PIO_PSR; // PIO Status Register
358 AT91_REG Reserved0[1]; //
359 AT91_REG PIO_OER; // Output Enable Register
360 AT91_REG PIO_ODR; // Output Disable Registerr
361 AT91_REG PIO_OSR; // Output Status Register
362 AT91_REG Reserved1[1]; //
363 AT91_REG PIO_IFER; // Input Filter Enable Register
364 AT91_REG PIO_IFDR; // Input Filter Disable Register
365 AT91_REG PIO_IFSR; // Input Filter Status Register
366 AT91_REG Reserved2[1]; //
367 AT91_REG PIO_SODR; // Set Output Data Register
368 AT91_REG PIO_CODR; // Clear Output Data Register
369 AT91_REG PIO_ODSR; // Output Data Status Register
370 AT91_REG PIO_PDSR; // Pin Data Status Register
371 AT91_REG PIO_IER; // Interrupt Enable Register
372 AT91_REG PIO_IDR; // Interrupt Disable Register
373 AT91_REG PIO_IMR; // Interrupt Mask Register
374 AT91_REG PIO_ISR; // Interrupt Status Register
375 AT91_REG PIO_MDER; // Multi-driver Enable Register
376 AT91_REG PIO_MDDR; // Multi-driver Disable Register
377 AT91_REG PIO_MDSR; // Multi-driver Status Register
378 AT91_REG Reserved3[1]; //
379 AT91_REG PIO_PPUDR; // Pull-up Disable Register
380 AT91_REG PIO_PPUER; // Pull-up Enable Register
381 AT91_REG PIO_PPUSR; // Pull-up Status Register
382 AT91_REG Reserved4[1]; //
383 AT91_REG PIO_ASR; // Select A Register
384 AT91_REG PIO_BSR; // Select B Register
385 AT91_REG PIO_ABSR; // AB Select Status Register
386 AT91_REG Reserved5[9]; //
387 AT91_REG PIO_OWER; // Output Write Enable Register
388 AT91_REG PIO_OWDR; // Output Write Disable Register
389 AT91_REG PIO_OWSR; // Output Write Status Register
397 AT91_REG CKGR_MOR; // Main Oscillator Register
398 AT91_REG CKGR_MCFR; // Main Clock Frequency Register
399 AT91_REG Reserved0[1]; //
400 AT91_REG CKGR_PLLR; // PLL Register
430 AT91_REG PMC_SCER; // System Clock Enable Register
431 AT91_REG PMC_SCDR; // System Clock Disable Register
432 AT91_REG PMC_SCSR; // System Clock Status Register
433 AT91_REG Reserved0[1]; //
434 AT91_REG PMC_PCER; // Peripheral Clock Enable Register
435 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
436 AT91_REG PMC_PCSR; // Peripheral Clock Status Register
437 AT91_REG Reserved1[1]; //
438 AT91_REG PMC_MOR; // Main Oscillator Register
439 AT91_REG PMC_MCFR; // Main Clock Frequency Register
440 AT91_REG Reserved2[1]; //
441 AT91_REG PMC_PLLR; // PLL Register
442 AT91_REG PMC_MCKR; // Master Clock Register
443 AT91_REG Reserved3[3]; //
444 AT91_REG PMC_PCKR[4]; // Programmable Clock Register
445 AT91_REG Reserved4[4]; //
446 AT91_REG PMC_IER; // Interrupt Enable Register
447 AT91_REG PMC_IDR; // Interrupt Disable Register
448 AT91_REG PMC_SR; // Status Register
449 AT91_REG PMC_IMR; // Interrupt Mask Register
494 AT91_REG RSTC_RCR; // Reset Control Register
495 AT91_REG RSTC_RSR; // Reset Status Register
496 AT91_REG RSTC_RMR; // Reset Mode Register
526 AT91_REG RTTC_RTMR; // Real-time Mode Register
527 AT91_REG RTTC_RTAR; // Real-time Alarm Register
528 AT91_REG RTTC_RTVR; // Real-time Value Register
529 AT91_REG RTTC_RTSR; // Real-time Status Register
549 AT91_REG PITC_PIMR; // Period Interval Mode Register
550 AT91_REG PITC_PISR; // Period Interval Status Register
551 AT91_REG PITC_PIVR; // Period Interval Value Register
552 AT91_REG PITC_PIIR; // Period Interval Image Register
570 AT91_REG WDTC_WDCR; // Watchdog Control Register
571 AT91_REG WDTC_WDMR; // Watchdog Mode Register
572 AT91_REG WDTC_WDSR; // Watchdog Status Register
595 AT91_REG VREG_MR; // Voltage Regulator Mode Register
605 AT91_REG MC_RCR; // MC Remap Control Register
606 AT91_REG MC_ASR; // MC Abort Status Register
607 AT91_REG MC_AASR; // MC Abort Address Status Register
608 AT91_REG Reserved0[21]; //
609 AT91_REG MC_FMR; // MC Flash Mode Register
610 AT91_REG MC_FCR; // MC Flash Command Register
611 AT91_REG MC_FSR; // MC Flash Status Register
685 AT91_REG SPI_CR; // Control Register
686 AT91_REG SPI_MR; // Mode Register
687 AT91_REG SPI_RDR; // Receive Data Register
688 AT91_REG SPI_TDR; // Transmit Data Register
689 AT91_REG SPI_SR; // Status Register
690 AT91_REG SPI_IER; // Interrupt Enable Register
691 AT91_REG SPI_IDR; // Interrupt Disable Register
692 AT91_REG SPI_IMR; // Interrupt Mask Register
693 AT91_REG Reserved0[4]; //
694 AT91_REG SPI_CSR[4]; // Chip Select Register
695 AT91_REG Reserved1[48]; //
696 AT91_REG SPI_RPR; // Receive Pointer Register
697 AT91_REG SPI_RCR; // Receive Counter Register
698 AT91_REG SPI_TPR; // Transmit Pointer Register
699 AT91_REG SPI_TCR; // Transmit Counter Register
700 AT91_REG SPI_RNPR; // Receive Next Pointer Register
701 AT91_REG SPI_RNCR; // Receive Next Counter Register
702 AT91_REG SPI_TNPR; // Transmit Next Pointer Register
703 AT91_REG SPI_TNCR; // Transmit Next Counter Register
704 AT91_REG SPI_PTCR; // PDC Transfer Control Register
705 AT91_REG SPI_PTSR; // PDC Transfer Status Register
767 AT91_REG US_CR; // Control Register
768 AT91_REG US_MR; // Mode Register
769 AT91_REG US_IER; // Interrupt Enable Register
770 AT91_REG US_IDR; // Interrupt Disable Register
771 AT91_REG US_IMR; // Interrupt Mask Register
772 AT91_REG US_CSR; // Channel Status Register
773 AT91_REG US_RHR; // Receiver Holding Register
774 AT91_REG US_THR; // Transmitter Holding Register
775 AT91_REG US_BRGR; // Baud Rate Generator Register
776 AT91_REG US_RTOR; // Receiver Time-out Register
777 AT91_REG US_TTGR; // Transmitter Time-guard Register
778 AT91_REG Reserved0[5]; //
779 AT91_REG US_FIDI; // FI_DI_Ratio Register
780 AT91_REG US_NER; // Nb Errors Register
781 AT91_REG Reserved1[1]; //
782 AT91_REG US_IF; // IRDA_FILTER Register
783 AT91_REG Reserved2[44]; //
784 AT91_REG US_RPR; // Receive Pointer Register
785 AT91_REG US_RCR; // Receive Counter Register
786 AT91_REG US_TPR; // Transmit Pointer Register
787 AT91_REG US_TCR; // Transmit Counter Register
788 AT91_REG US_RNPR; // Receive Next Pointer Register
789 AT91_REG US_RNCR; // Receive Next Counter Register
790 AT91_REG US_TNPR; // Transmit Next Pointer Register
791 AT91_REG US_TNCR; // Transmit Next Counter Register
792 AT91_REG US_PTCR; // PDC Transfer Control Register
793 AT91_REG US_PTSR; // PDC Transfer Status Register
862 AT91_REG SSC_CR; // Control Register
863 AT91_REG SSC_CMR; // Clock Mode Register
864 AT91_REG Reserved0[2]; //
865 AT91_REG SSC_RCMR; // Receive Clock ModeRegister
866 AT91_REG SSC_RFMR; // Receive Frame Mode Register
867 AT91_REG SSC_TCMR; // Transmit Clock Mode Register
868 AT91_REG SSC_TFMR; // Transmit Frame Mode Register
869 AT91_REG SSC_RHR; // Receive Holding Register
870 AT91_REG SSC_THR; // Transmit Holding Register
871 AT91_REG Reserved1[2]; //
872 AT91_REG SSC_RSHR; // Receive Sync Holding Register
873 AT91_REG SSC_TSHR; // Transmit Sync Holding Register
874 AT91_REG Reserved2[2]; //
875 AT91_REG SSC_SR; // Status Register
876 AT91_REG SSC_IER; // Interrupt Enable Register
877 AT91_REG SSC_IDR; // Interrupt Disable Register
878 AT91_REG SSC_IMR; // Interrupt Mask Register
879 AT91_REG Reserved3[44]; //
880 AT91_REG SSC_RPR; // Receive Pointer Register
881 AT91_REG SSC_RCR; // Receive Counter Register
882 AT91_REG SSC_TPR; // Transmit Pointer Register
883 AT91_REG SSC_TCR; // Transmit Counter Register
884 AT91_REG SSC_RNPR; // Receive Next Pointer Register
885 AT91_REG SSC_RNCR; // Receive Next Counter Register
886 AT91_REG SSC_TNPR; // Transmit Next Pointer Register
887 AT91_REG SSC_TNCR; // Transmit Next Counter Register
888 AT91_REG SSC_PTCR; // PDC Transfer Control Register
889 AT91_REG SSC_PTSR; // PDC Transfer Status Register
959 AT91_REG TWI_CR; // Control Register
960 AT91_REG TWI_MMR; // Master Mode Register
961 AT91_REG Reserved0[1]; //
962 AT91_REG TWI_IADR; // Internal Address Register
963 AT91_REG TWI_CWGR; // Clock Waveform Generator Register
964 AT91_REG Reserved1[3]; //
965 AT91_REG TWI_SR; // Status Register
966 AT91_REG TWI_IER; // Interrupt Enable Register
967 AT91_REG TWI_IDR; // Interrupt Disable Register
968 AT91_REG TWI_IMR; // Interrupt Mask Register
969 AT91_REG TWI_RHR; // Receive Holding Register
970 AT91_REG TWI_THR; // Transmit Holding Register
1006 AT91_REG PWMC_CMR; // Channel Mode Register
1007 AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
1008 AT91_REG PWMC_CPRDR; // Channel Period Register
1009 AT91_REG PWMC_CCNTR; // Channel Counter Register
1010 AT91_REG PWMC_CUPDR; // Channel Update Register
1011 AT91_REG PWMC_Reserved[3]; // Reserved
1035 AT91_REG PWMC_MR; // PWMC Mode Register
1036 AT91_REG PWMC_ENA; // PWMC Enable Register
1037 AT91_REG PWMC_DIS; // PWMC Disable Register
1038 AT91_REG PWMC_SR; // PWMC Status Register
1039 AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
1040 AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
1041 AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
1042 AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
1043 AT91_REG Reserved0[55]; //
1044 AT91_REG PWMC_VR; // PWMC Version Register
1045 AT91_REG Reserved1[64]; //
1072 AT91_REG UDP_NUM; // Frame Number Register
1073 AT91_REG UDP_GLBSTATE; // Global State Register
1074 AT91_REG UDP_FADDR; // Function Address Register
1075 AT91_REG Reserved0[1]; //
1076 AT91_REG UDP_IER; // Interrupt Enable Register
1077 AT91_REG UDP_IDR; // Interrupt Disable Register
1078 AT91_REG UDP_IMR; // Interrupt Mask Register
1079 AT91_REG UDP_ISR; // Interrupt Status Register
1080 AT91_REG UDP_ICR; // Interrupt Clear Register
1081 AT91_REG Reserved1[1]; //
1082 AT91_REG UDP_RSTEP; // Reset Endpoint Register
1083 AT91_REG Reserved2[1]; //
1084 AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
1085 AT91_REG Reserved3[2]; //
1086 AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
1087 AT91_REG Reserved4[3]; //
1088 AT91_REG UDP_TXVC; // Transceiver Control Register
1156 AT91_REG TC_CCR; // Channel Control Register
1157 AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
1158 AT91_REG Reserved0[2]; //
1159 AT91_REG TC_CV; // Counter Value
1160 AT91_REG TC_RA; // Register A
1161 AT91_REG TC_RB; // Register B
1162 AT91_REG TC_RC; // Register C
1163 AT91_REG TC_SR; // Status Register
1164 AT91_REG TC_IER; // Interrupt Enable Register
1165 AT91_REG TC_IDR; // Interrupt Disable Register
1166 AT91_REG TC_IMR; // Interrupt Mask Register
1288 AT91_REG Reserved0[4]; //
1290 AT91_REG Reserved1[4]; //
1292 AT91_REG Reserved2[4]; //
1293 AT91_REG TCB_BCR; // TC Block Control Register
1294 AT91_REG TCB_BMR; // TC Block Mode Register
1320 AT91_REG CAN_MB_MMR; // MailBox Mode Register
1321 AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
1322 AT91_REG CAN_MB_MID; // MailBox ID Register
1323 AT91_REG CAN_MB_MFID; // MailBox Family ID Register
1324 AT91_REG CAN_MB_MSR; // MailBox Status Register
1325 AT91_REG CAN_MB_MDL; // MailBox Data Low Register
1326 AT91_REG CAN_MB_MDH; // MailBox Data High Register
1327 AT91_REG CAN_MB_MCR; // MailBox Control Register
1363 AT91_REG CAN_MR; // Mode Register
1364 AT91_REG CAN_IER; // Interrupt Enable Register
1365 AT91_REG CAN_IDR; // Interrupt Disable Register
1366 AT91_REG CAN_IMR; // Interrupt Mask Register
1367 AT91_REG CAN_SR; // Status Register
1368 AT91_REG CAN_BR; // Baudrate Register
1369 AT91_REG CAN_TIM; // Timer Register
1370 AT91_REG CAN_TIMESTP; // Time Stamp Register
1371 AT91_REG CAN_ECR; // Error Counter Register
1372 AT91_REG CAN_TCR; // Transfer Command Register
1373 AT91_REG CAN_ACR; // Abort Command Register
1374 AT91_REG Reserved0[52]; //
1375 AT91_REG CAN_VR; // Version Register
1376 AT91_REG Reserved1[64]; //
1461 AT91_REG EMAC_NCR; // Network Control Register
1462 AT91_REG EMAC_NCFGR; // Network Configuration Register
1463 AT91_REG EMAC_NSR; // Network Status Register
1464 AT91_REG Reserved0[2]; //
1465 AT91_REG EMAC_TSR; // Transmit Status Register
1466 AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
1467 AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
1468 AT91_REG EMAC_RSR; // Receive Status Register
1469 AT91_REG EMAC_ISR; // Interrupt Status Register
1470 AT91_REG EMAC_IER; // Interrupt Enable Register
1471 AT91_REG EMAC_IDR; // Interrupt Disable Register
1472 AT91_REG EMAC_IMR; // Interrupt Mask Register
1473 AT91_REG EMAC_MAN; // PHY Maintenance Register
1474 AT91_REG EMAC_PTR; // Pause Time Register
1475 AT91_REG EMAC_PFR; // Pause Frames received Register
1476 AT91_REG EMAC_FTO; // Frames Transmitted OK Register
1477 AT91_REG EMAC_SCF; // Single Collision Frame Register
1478 AT91_REG EMAC_MCF; // Multiple Collision Frame Register
1479 AT91_REG EMAC_FRO; // Frames Received OK Register
1480 AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
1481 AT91_REG EMAC_ALE; // Alignment Error Register
1482 AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
1483 AT91_REG EMAC_LCOL; // Late Collision Register
1484 AT91_REG EMAC_ECOL; // Excessive Collision Register
1485 AT91_REG EMAC_TUND; // Transmit Underrun Error Register
1486 AT91_REG EMAC_CSE; // Carrier Sense Error Register
1487 AT91_REG EMAC_RRE; // Receive Ressource Error Register
1488 AT91_REG EMAC_ROV; // Receive Overrun Errors Register
1489 AT91_REG EMAC_RSE; // Receive Symbol Errors Register
1490 AT91_REG EMAC_ELE; // Excessive Length Errors Register
1491 AT91_REG EMAC_RJA; // Receive Jabbers Register
1492 AT91_REG EMAC_USF; // Undersize Frames Register
1493 AT91_REG EMAC_STE; // SQE Test Error Register
1494 AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
1495 AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
1496 AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
1497 AT91_REG EMAC_HRT; // Hash Address Top[63:32]
1498 AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
1499 AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
1500 AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
1501 AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
1502 AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
1503 AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
1504 AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
1505 AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
1506 AT91_REG EMAC_TID; // Type ID Checking Register
1507 AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
1508 AT91_REG EMAC_USRIO; // USER Input/Output Register
1509 AT91_REG EMAC_WOL; // Wake On LAN Register
1510 AT91_REG Reserved1[13]; //
1511 AT91_REG EMAC_REV; // Revision Register
1609 AT91_REG ADC_CR; // ADC Control Register
1610 AT91_REG ADC_MR; // ADC Mode Register
1611 AT91_REG Reserved0[2]; //
1612 AT91_REG ADC_CHER; // ADC Channel Enable Register
1613 AT91_REG ADC_CHDR; // ADC Channel Disable Register
1614 AT91_REG ADC_CHSR; // ADC Channel Status Register
1615 AT91_REG ADC_SR; // ADC Status Register
1616 AT91_REG ADC_LCDR; // ADC Last Converted Data Register
1617 AT91_REG ADC_IER; // ADC Interrupt Enable Register
1618 AT91_REG ADC_IDR; // ADC Interrupt Disable Register
1619 AT91_REG ADC_IMR; // ADC Interrupt Mask Register
1620 AT91_REG ADC_CDR0; // ADC Channel Data Register 0
1621 AT91_REG ADC_CDR1; // ADC Channel Data Register 1
1622 AT91_REG ADC_CDR2; // ADC Channel Data Register 2
1623 AT91_REG ADC_CDR3; // ADC Channel Data Register 3
1624 AT91_REG ADC_CDR4; // ADC Channel Data Register 4
1625 AT91_REG ADC_CDR5; // ADC Channel Data Register 5
1626 AT91_REG ADC_CDR6; // ADC Channel Data Register 6
1627 AT91_REG ADC_CDR7; // ADC Channel Data Register 7
1628 AT91_REG Reserved1[44]; //
1629 AT91_REG ADC_RPR; // Receive Pointer Register
1630 AT91_REG ADC_RCR; // Receive Counter Register
1631 AT91_REG ADC_TPR; // Transmit Pointer Register
1632 AT91_REG ADC_TCR; // Transmit Counter Register
1633 AT91_REG ADC_RNPR; // Receive Next Pointer Register
1634 AT91_REG ADC_RNCR; // Receive Next Counter Register
1635 AT91_REG ADC_TNPR; // Transmit Next Pointer Register
1636 AT91_REG ADC_TNCR; // Transmit Next Counter Register
1637 AT91_REG ADC_PTCR; // PDC Transfer Control Register
1638 AT91_REG ADC_PTSR; // PDC Transfer Status Register
1716 AT91_REG AES_CR; // Control Register
1717 AT91_REG AES_MR; // Mode Register
1718 AT91_REG Reserved0[2]; //
1719 AT91_REG AES_IER; // Interrupt Enable Register
1720 AT91_REG AES_IDR; // Interrupt Disable Register
1721 AT91_REG AES_IMR; // Interrupt Mask Register
1722 AT91_REG AES_ISR; // Interrupt Status Register
1723 AT91_REG AES_KEYWxR[4]; // Key Word x Register
1724 AT91_REG Reserved1[4]; //
1725 AT91_REG AES_IDATAxR[4]; // Input Data x Register
1726 AT91_REG AES_ODATAxR[4]; // Output Data x Register
1727 AT91_REG AES_IVxR[4]; // Initialization Vector x Register
1728 AT91_REG Reserved2[35]; //
1729 AT91_REG AES_VR; // AES Version Register
1730 AT91_REG AES_RPR; // Receive Pointer Register
1731 AT91_REG AES_RCR; // Receive Counter Register
1732 AT91_REG AES_TPR; // Transmit Pointer Register
1733 AT91_REG AES_TCR; // Transmit Counter Register
1734 AT91_REG AES_RNPR; // Receive Next Pointer Register
1735 AT91_REG AES_RNCR; // Receive Next Counter Register
1736 AT91_REG AES_TNPR; // Transmit Next Pointer Register
1737 AT91_REG AES_TNCR; // Transmit Next Counter Register
1738 AT91_REG AES_PTCR; // PDC Transfer Control Register
1739 AT91_REG AES_PTSR; // PDC Transfer Status Register
1795 AT91_REG TDES_CR; // Control Register
1796 AT91_REG TDES_MR; // Mode Register
1797 AT91_REG Reserved0[2]; //
1798 AT91_REG TDES_IER; // Interrupt Enable Register
1799 AT91_REG TDES_IDR; // Interrupt Disable Register
1800 AT91_REG TDES_IMR; // Interrupt Mask Register
1801 AT91_REG TDES_ISR; // Interrupt Status Register
1802 AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register
1803 AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register
1804 AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register
1805 AT91_REG Reserved1[2]; //
1806 AT91_REG TDES_IDATAxR[2]; // Input Data x Register
1807 AT91_REG Reserved2[2]; //
1808 AT91_REG TDES_ODATAxR[2]; // Output Data x Register
1809 AT91_REG Reserved3[2]; //
1810 AT91_REG TDES_IVxR[2]; // Initialization Vector x Register
1811 AT91_REG Reserved4[37]; //
1812 AT91_REG TDES_VR; // TDES Version Register
1813 AT91_REG TDES_RPR; // Receive Pointer Register
1814 AT91_REG TDES_RCR; // Receive Counter Register
1815 AT91_REG TDES_TPR; // Transmit Pointer Register
1816 AT91_REG TDES_TCR; // Transmit Counter Register
1817 AT91_REG TDES_RNPR; // Receive Next Pointer Register
1818 AT91_REG TDES_RNCR; // Receive Next Counter Register
1819 AT91_REG TDES_TNPR; // Transmit Next Pointer Register
1820 AT91_REG TDES_TNCR; // Transmit Next Counter Register
1821 AT91_REG TDES_PTCR; // PDC Transfer Control Register
1822 AT91_REG TDES_PTSR; // PDC Transfer Status Register
1868 #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
1869 #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
1870 #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
1871 #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
1872 #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
1873 #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
1874 #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
1875 #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
1876 #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
1877 #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
1878 #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
1879 #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
1880 #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
1881 #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
1882 #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
1883 #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
1884 #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
1885 #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
1887 #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1888 #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1889 #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1890 #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1891 #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1892 #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1893 #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1894 #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1895 #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1896 #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1898 #define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
1899 #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
1900 #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
1901 #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
1902 #define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
1903 #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
1904 #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
1905 #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
1906 #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
1907 #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
1908 #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
1909 #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
1911 #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
1912 #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
1913 #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
1914 #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
1915 #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
1916 #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
1917 #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
1918 #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
1919 #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
1920 #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
1921 #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
1922 #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
1923 #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
1924 #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
1925 #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
1926 #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
1927 #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
1928 #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
1929 #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
1930 #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
1931 #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
1932 #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
1933 #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
1934 #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
1935 #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
1936 #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
1937 #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
1938 #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
1939 #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
1941 #define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
1942 #define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
1943 #define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
1944 #define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
1945 #define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
1946 #define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
1947 #define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
1948 #define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
1949 #define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
1950 #define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
1951 #define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
1952 #define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
1953 #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
1954 #define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
1955 #define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
1956 #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
1957 #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
1958 #define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
1959 #define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
1960 #define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
1961 #define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
1962 #define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
1963 #define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
1964 #define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
1965 #define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
1966 #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
1967 #define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
1968 #define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
1969 #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
1971 #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
1972 #define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
1973 #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
1975 #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
1976 #define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
1977 #define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
1978 #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1979 #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
1980 #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
1981 #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
1982 #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
1983 #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
1984 #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
1985 #define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
1986 #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
1987 #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
1988 #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
1989 #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
1991 #define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
1992 #define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
1993 #define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
1995 #define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
1996 #define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
1997 #define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
1998 #define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
2000 #define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
2001 #define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
2002 #define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
2003 #define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
2005 #define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
2006 #define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
2007 #define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
2009 #define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
2011 #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
2012 #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
2013 #define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
2014 #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
2015 #define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
2016 #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
2018 #define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
2019 #define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
2020 #define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
2021 #define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
2022 #define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
2023 #define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
2024 #define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
2025 #define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
2026 #define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
2027 #define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
2029 #define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
2030 #define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
2031 #define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
2032 #define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
2033 #define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
2034 #define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
2035 #define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
2036 #define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
2037 #define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
2039 #define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
2040 #define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
2041 #define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
2042 #define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
2043 #define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
2044 #define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
2045 #define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
2046 #define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
2047 #define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
2048 #define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
2050 #define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
2051 #define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
2052 #define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
2053 #define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
2054 #define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
2055 #define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
2056 #define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
2057 #define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
2058 #define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
2060 #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
2061 #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
2062 #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
2063 #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
2064 #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
2065 #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
2066 #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
2067 #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
2068 #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
2069 #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
2071 #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
2072 #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
2073 #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
2074 #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
2075 #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
2076 #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
2077 #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
2078 #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
2079 #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
2080 #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
2081 #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
2082 #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
2083 #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
2084 #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
2086 #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
2087 #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
2088 #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
2089 #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
2090 #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
2091 #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
2092 #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
2093 #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
2094 #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
2095 #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
2097 #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
2098 #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
2099 #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
2100 #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
2101 #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
2102 #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
2103 #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
2104 #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
2105 #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
2106 #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
2107 #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
2108 #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
2109 #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
2110 #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
2112 #define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
2113 #define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
2114 #define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
2115 #define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
2116 #define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
2117 #define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
2118 #define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
2119 #define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
2120 #define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
2121 #define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
2123 #define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
2124 #define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
2125 #define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
2126 #define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
2127 #define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
2128 #define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
2129 #define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
2130 #define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
2131 #define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
2132 #define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
2133 #define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
2134 #define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
2135 #define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
2136 #define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
2138 #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
2139 #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
2140 #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
2141 #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
2142 #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
2143 #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
2144 #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
2145 #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
2146 #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
2147 #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
2149 #define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
2150 #define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
2151 #define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
2152 #define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
2153 #define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
2154 #define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
2156 #define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
2157 #define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
2158 #define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
2159 #define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
2160 #define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
2161 #define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
2163 #define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
2164 #define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
2165 #define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
2166 #define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
2167 #define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
2168 #define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
2170 #define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
2171 #define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
2172 #define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
2173 #define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
2174 #define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
2175 #define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
2177 #define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
2178 #define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
2179 #define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
2180 #define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
2181 #define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
2182 #define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
2183 #define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
2184 #define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
2185 #define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
2187 #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
2188 #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
2189 #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
2190 #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
2191 #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
2192 #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
2193 #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
2194 #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
2195 #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
2196 #define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
2197 #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
2198 #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
2200 #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
2201 #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
2202 #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
2203 #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
2204 #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / …
2205 #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
2206 #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
2207 #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
2208 #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
2209 #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
2211 #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
2212 #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
2213 #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
2214 #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
2215 #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
2216 #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / …
2217 #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
2218 #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
2219 #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
2220 #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
2222 #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / …
2223 #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
2224 #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
2225 #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
2226 #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
2227 #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
2228 #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
2229 #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
2230 #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
2231 #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
2233 #define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
2234 #define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
2236 #define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
2237 #define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Regist…
2238 #define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
2239 #define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
2240 #define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
2241 #define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
2242 #define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
2243 #define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
2245 #define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
2246 #define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
2247 #define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
2248 #define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
2249 #define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Regist…
2250 #define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
2251 #define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
2252 #define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
2254 #define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
2255 #define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
2256 #define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
2257 #define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
2258 #define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
2259 #define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Regist…
2260 #define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
2261 #define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
2263 #define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
2264 #define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Regist…
2265 #define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
2266 #define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
2267 #define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
2268 #define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
2269 #define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
2270 #define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
2272 #define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
2273 #define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
2274 #define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
2275 #define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
2276 #define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
2277 #define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
2278 #define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
2279 #define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Regist…
2281 #define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
2282 #define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
2283 #define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
2284 #define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
2285 #define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
2286 #define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
2287 #define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
2288 #define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Regist…
2290 #define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
2291 #define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
2292 #define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Regist…
2293 #define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
2294 #define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
2295 #define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
2296 #define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
2297 #define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
2299 #define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
2300 #define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
2301 #define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
2302 #define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
2303 #define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
2304 #define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
2305 #define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Regist…
2306 #define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
2308 #define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
2309 #define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
2310 #define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
2311 #define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
2312 #define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
2313 #define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
2314 #define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
2315 #define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
2316 #define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
2317 #define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register
2318 #define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
2319 #define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
2321 #define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
2322 #define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
2323 #define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 by…
2324 #define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
2325 #define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
2326 #define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
2327 #define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
2328 #define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
2329 #define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
2330 #define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
2331 #define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 by…
2332 #define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
2333 #define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 by…
2334 #define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
2335 #define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
2336 #define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
2337 #define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
2338 #define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
2339 #define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
2340 #define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
2341 #define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
2342 #define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
2343 #define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
2344 #define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
2345 #define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
2346 #define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
2347 #define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
2348 #define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
2349 #define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
2350 #define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
2351 #define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
2352 #define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
2353 #define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
2354 #define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
2355 #define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
2356 #define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
2357 #define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
2358 #define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
2359 #define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
2360 #define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
2361 #define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
2362 #define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 by…
2363 #define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
2364 #define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
2365 #define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
2366 #define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
2367 #define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
2368 #define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
2369 #define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
2371 #define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
2372 #define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
2373 #define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
2374 #define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
2375 #define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
2376 #define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
2377 #define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
2378 #define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
2379 #define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
2380 #define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
2382 #define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
2383 #define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
2384 #define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
2385 #define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
2386 #define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
2387 #define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
2388 #define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
2389 #define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
2390 #define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
2391 #define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
2392 #define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
2393 #define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
2394 #define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
2395 #define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
2396 #define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
2397 #define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
2398 #define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
2399 #define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
2401 #define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register
2402 #define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
2403 #define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
2404 #define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
2405 #define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register
2406 #define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register
2407 #define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register
2408 #define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
2409 #define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register
2410 #define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
2412 #define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register
2413 #define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register
2414 #define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register
2415 #define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register
2416 #define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register
2417 #define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register
2418 #define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register
2419 #define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register
2420 #define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register
2421 #define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register
2422 #define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register
2424 #define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
2425 #define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register
2426 #define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register
2427 #define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
2428 #define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
2429 #define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register
2430 #define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
2431 #define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
2432 #define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
2433 #define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
2435 #define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register
2436 #define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register
2437 #define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register
2438 #define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register
2439 #define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register
2440 #define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register
2441 #define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register
2442 #define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register
2443 #define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register
2444 #define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register
2445 #define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register
2446 #define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register
2447 #define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register