Lines Matching refs:AT91_REG
35 typedef volatile unsigned int AT91_REG;// Hardware register definition typedef
41 AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register
42 AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register
43 AT91_REG SYSC_AIC_IVR; // IRQ Vector Register
44 AT91_REG SYSC_AIC_FVR; // FIQ Vector Register
45 AT91_REG SYSC_AIC_ISR; // Interrupt Status Register
46 AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register
47 AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register
48 AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register
49 AT91_REG Reserved0[2]; //
50 AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register
51 AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register
52 AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register
53 AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register
54 AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register
55 AT91_REG SYSC_AIC_SPU; // Spurious Vector Register
56 AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect)
57 AT91_REG Reserved1[1]; //
58 AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register
59 AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register
60 AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register
61 AT91_REG Reserved2[45]; //
62 AT91_REG SYSC_DBGU_CR; // Control Register
63 AT91_REG SYSC_DBGU_MR; // Mode Register
64 AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register
65 AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register
66 AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register
67 AT91_REG SYSC_DBGU_CSR; // Channel Status Register
68 AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register
69 AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register
70 AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register
71 AT91_REG Reserved3[7]; //
72 AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register
73 AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register
74 AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register
75 AT91_REG Reserved4[45]; //
76 AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register
77 AT91_REG SYSC_DBGU_RCR; // Receive Counter Register
78 AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register
79 AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register
80 AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register
81 AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register
82 AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register
83 AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register
84 AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register
85 AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register
86 AT91_REG Reserved5[54]; //
87 AT91_REG SYSC_PIOA_PER; // PIO Enable Register
88 AT91_REG SYSC_PIOA_PDR; // PIO Disable Register
89 AT91_REG SYSC_PIOA_PSR; // PIO Status Register
90 AT91_REG Reserved6[1]; //
91 AT91_REG SYSC_PIOA_OER; // Output Enable Register
92 AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr
93 AT91_REG SYSC_PIOA_OSR; // Output Status Register
94 AT91_REG Reserved7[1]; //
95 AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register
96 AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register
97 AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register
98 AT91_REG Reserved8[1]; //
99 AT91_REG SYSC_PIOA_SODR; // Set Output Data Register
100 AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register
101 AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register
102 AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register
103 AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register
104 AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register
105 AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register
106 AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register
107 AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register
108 AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register
109 AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register
110 AT91_REG Reserved9[1]; //
111 AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register
112 AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register
113 AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register
114 AT91_REG Reserved10[1]; //
115 AT91_REG SYSC_PIOA_ASR; // Select A Register
116 AT91_REG SYSC_PIOA_BSR; // Select B Register
117 AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register
118 AT91_REG Reserved11[9]; //
119 AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register
120 AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register
121 AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register
122 AT91_REG Reserved12[469]; //
123 AT91_REG SYSC_PMC_SCER; // System Clock Enable Register
124 AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register
125 AT91_REG SYSC_PMC_SCSR; // System Clock Status Register
126 AT91_REG Reserved13[1]; //
127 AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register
128 AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register
129 AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register
130 AT91_REG Reserved14[1]; //
131 AT91_REG SYSC_PMC_MOR; // Main Oscillator Register
132 AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register
133 AT91_REG Reserved15[1]; //
134 AT91_REG SYSC_PMC_PLLR; // PLL Register
135 AT91_REG SYSC_PMC_MCKR; // Master Clock Register
136 AT91_REG Reserved16[3]; //
137 AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register
138 AT91_REG SYSC_PMC_IER; // Interrupt Enable Register
139 AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register
140 AT91_REG SYSC_PMC_SR; // Status Register
141 AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register
142 AT91_REG Reserved17[36]; //
143 AT91_REG SYSC_RSTC_RCR; // Reset Control Register
144 AT91_REG SYSC_RSTC_RSR; // Reset Status Register
145 AT91_REG SYSC_RSTC_RMR; // Reset Mode Register
146 AT91_REG Reserved18[5]; //
147 AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register
148 AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register
149 AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register
150 AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register
151 AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register
152 AT91_REG SYSC_PITC_PISR; // Period Interval Status Register
153 AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register
154 AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register
155 AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register
156 AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register
157 AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register
158 AT91_REG Reserved19[5]; //
159 AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register
169 AT91_REG AIC_SMR[32]; // Source Mode Register
170 AT91_REG AIC_SVR[32]; // Source Vector Register
171 AT91_REG AIC_IVR; // IRQ Vector Register
172 AT91_REG AIC_FVR; // FIQ Vector Register
173 AT91_REG AIC_ISR; // Interrupt Status Register
174 AT91_REG AIC_IPR; // Interrupt Pending Register
175 AT91_REG AIC_IMR; // Interrupt Mask Register
176 AT91_REG AIC_CISR; // Core Interrupt Status Register
177 AT91_REG Reserved0[2]; //
178 AT91_REG AIC_IECR; // Interrupt Enable Command Register
179 AT91_REG AIC_IDCR; // Interrupt Disable Command Register
180 AT91_REG AIC_ICCR; // Interrupt Clear Command Register
181 AT91_REG AIC_ISCR; // Interrupt Set Command Register
182 AT91_REG AIC_EOICR; // End of Interrupt Command Register
183 AT91_REG AIC_SPU; // Spurious Vector Register
184 AT91_REG AIC_DCR; // Debug Control Register (Protect)
185 AT91_REG Reserved1[1]; //
186 AT91_REG AIC_FFER; // Fast Forcing Enable Register
187 AT91_REG AIC_FFDR; // Fast Forcing Disable Register
188 AT91_REG AIC_FFSR; // Fast Forcing Status Register
211 AT91_REG DBGU_CR; // Control Register
212 AT91_REG DBGU_MR; // Mode Register
213 AT91_REG DBGU_IER; // Interrupt Enable Register
214 AT91_REG DBGU_IDR; // Interrupt Disable Register
215 AT91_REG DBGU_IMR; // Interrupt Mask Register
216 AT91_REG DBGU_CSR; // Channel Status Register
217 AT91_REG DBGU_RHR; // Receiver Holding Register
218 AT91_REG DBGU_THR; // Transmitter Holding Register
219 AT91_REG DBGU_BRGR; // Baud Rate Generator Register
220 AT91_REG Reserved0[7]; //
221 AT91_REG DBGU_C1R; // Chip ID1 Register
222 AT91_REG DBGU_C2R; // Chip ID2 Register
223 AT91_REG DBGU_FNTR; // Force NTRST Register
224 AT91_REG Reserved1[45]; //
225 AT91_REG DBGU_RPR; // Receive Pointer Register
226 AT91_REG DBGU_RCR; // Receive Counter Register
227 AT91_REG DBGU_TPR; // Transmit Pointer Register
228 AT91_REG DBGU_TCR; // Transmit Counter Register
229 AT91_REG DBGU_RNPR; // Receive Next Pointer Register
230 AT91_REG DBGU_RNCR; // Receive Next Counter Register
231 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
232 AT91_REG DBGU_TNCR; // Transmit Next Counter Register
233 AT91_REG DBGU_PTCR; // PDC Transfer Control Register
234 AT91_REG DBGU_PTSR; // PDC Transfer Status Register
280 AT91_REG PDC_RPR; // Receive Pointer Register
281 AT91_REG PDC_RCR; // Receive Counter Register
282 AT91_REG PDC_TPR; // Transmit Pointer Register
283 AT91_REG PDC_TCR; // Transmit Counter Register
284 AT91_REG PDC_RNPR; // Receive Next Pointer Register
285 AT91_REG PDC_RNCR; // Receive Next Counter Register
286 AT91_REG PDC_TNPR; // Transmit Next Pointer Register
287 AT91_REG PDC_TNCR; // Transmit Next Counter Register
288 AT91_REG PDC_PTCR; // PDC Transfer Control Register
289 AT91_REG PDC_PTSR; // PDC Transfer Status Register
303 AT91_REG PIO_PER; // PIO Enable Register
304 AT91_REG PIO_PDR; // PIO Disable Register
305 AT91_REG PIO_PSR; // PIO Status Register
306 AT91_REG Reserved0[1]; //
307 AT91_REG PIO_OER; // Output Enable Register
308 AT91_REG PIO_ODR; // Output Disable Registerr
309 AT91_REG PIO_OSR; // Output Status Register
310 AT91_REG Reserved1[1]; //
311 AT91_REG PIO_IFER; // Input Filter Enable Register
312 AT91_REG PIO_IFDR; // Input Filter Disable Register
313 AT91_REG PIO_IFSR; // Input Filter Status Register
314 AT91_REG Reserved2[1]; //
315 AT91_REG PIO_SODR; // Set Output Data Register
316 AT91_REG PIO_CODR; // Clear Output Data Register
317 AT91_REG PIO_ODSR; // Output Data Status Register
318 AT91_REG PIO_PDSR; // Pin Data Status Register
319 AT91_REG PIO_IER; // Interrupt Enable Register
320 AT91_REG PIO_IDR; // Interrupt Disable Register
321 AT91_REG PIO_IMR; // Interrupt Mask Register
322 AT91_REG PIO_ISR; // Interrupt Status Register
323 AT91_REG PIO_MDER; // Multi-driver Enable Register
324 AT91_REG PIO_MDDR; // Multi-driver Disable Register
325 AT91_REG PIO_MDSR; // Multi-driver Status Register
326 AT91_REG Reserved3[1]; //
327 AT91_REG PIO_PPUDR; // Pull-up Disable Register
328 AT91_REG PIO_PPUER; // Pull-up Enable Register
329 AT91_REG PIO_PPUSR; // Pad Pull-up Status Register
330 AT91_REG Reserved4[1]; //
331 AT91_REG PIO_ASR; // Select A Register
332 AT91_REG PIO_BSR; // Select B Register
333 AT91_REG PIO_ABSR; // AB Select Status Register
334 AT91_REG Reserved5[9]; //
335 AT91_REG PIO_OWER; // Output Write Enable Register
336 AT91_REG PIO_OWDR; // Output Write Disable Register
337 AT91_REG PIO_OWSR; // Output Write Status Register
345 AT91_REG CKGR_MOR; // Main Oscillator Register
346 AT91_REG CKGR_MCFR; // Main Clock Frequency Register
347 AT91_REG Reserved0[1]; //
348 AT91_REG CKGR_PLLR; // PLL Register
378 AT91_REG PMC_SCER; // System Clock Enable Register
379 AT91_REG PMC_SCDR; // System Clock Disable Register
380 AT91_REG PMC_SCSR; // System Clock Status Register
381 AT91_REG Reserved0[1]; //
382 AT91_REG PMC_PCER; // Peripheral Clock Enable Register
383 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
384 AT91_REG PMC_PCSR; // Peripheral Clock Status Register
385 AT91_REG Reserved1[1]; //
386 AT91_REG PMC_MOR; // Main Oscillator Register
387 AT91_REG PMC_MCFR; // Main Clock Frequency Register
388 AT91_REG Reserved2[1]; //
389 AT91_REG PMC_PLLR; // PLL Register
390 AT91_REG PMC_MCKR; // Master Clock Register
391 AT91_REG Reserved3[3]; //
392 AT91_REG PMC_PCKR[8]; // Programmable Clock Register
393 AT91_REG PMC_IER; // Interrupt Enable Register
394 AT91_REG PMC_IDR; // Interrupt Disable Register
395 AT91_REG PMC_SR; // Status Register
396 AT91_REG PMC_IMR; // Interrupt Mask Register
441 AT91_REG RSTC_RCR; // Reset Control Register
442 AT91_REG RSTC_RSR; // Reset Status Register
443 AT91_REG RSTC_RMR; // Reset Mode Register
473 AT91_REG RTTC_RTMR; // Real-time Mode Register
474 AT91_REG RTTC_RTAR; // Real-time Alarm Register
475 AT91_REG RTTC_RTVR; // Real-time Value Register
476 AT91_REG RTTC_RTSR; // Real-time Status Register
496 AT91_REG PITC_PIMR; // Period Interval Mode Register
497 AT91_REG PITC_PISR; // Period Interval Status Register
498 AT91_REG PITC_PIVR; // Period Interval Value Register
499 AT91_REG PITC_PIIR; // Period Interval Image Register
517 AT91_REG WDTC_WDCR; // Watchdog Control Register
518 AT91_REG WDTC_WDMR; // Watchdog Mode Register
519 AT91_REG WDTC_WDSR; // Watchdog Status Register
541 AT91_REG MC_RCR; // MC Remap Control Register
542 AT91_REG MC_ASR; // MC Abort Status Register
543 AT91_REG MC_AASR; // MC Abort Address Status Register
544 AT91_REG Reserved0[21]; //
545 AT91_REG MC_FMR; // MC Flash Mode Register
546 AT91_REG MC_FCR; // MC Flash Command Register
547 AT91_REG MC_FSR; // MC Flash Status Register
621 AT91_REG SPI_CR; // Control Register
622 AT91_REG SPI_MR; // Mode Register
623 AT91_REG SPI_RDR; // Receive Data Register
624 AT91_REG SPI_TDR; // Transmit Data Register
625 AT91_REG SPI_SR; // Status Register
626 AT91_REG SPI_IER; // Interrupt Enable Register
627 AT91_REG SPI_IDR; // Interrupt Disable Register
628 AT91_REG SPI_IMR; // Interrupt Mask Register
629 AT91_REG Reserved0[4]; //
630 AT91_REG SPI_CSR[4]; // Chip Select Register
631 AT91_REG Reserved1[48]; //
632 AT91_REG SPI_RPR; // Receive Pointer Register
633 AT91_REG SPI_RCR; // Receive Counter Register
634 AT91_REG SPI_TPR; // Transmit Pointer Register
635 AT91_REG SPI_TCR; // Transmit Counter Register
636 AT91_REG SPI_RNPR; // Receive Next Pointer Register
637 AT91_REG SPI_RNCR; // Receive Next Counter Register
638 AT91_REG SPI_TNPR; // Transmit Next Pointer Register
639 AT91_REG SPI_TNCR; // Transmit Next Counter Register
640 AT91_REG SPI_PTCR; // PDC Transfer Control Register
641 AT91_REG SPI_PTSR; // PDC Transfer Status Register
703 AT91_REG ADC_CR; // ADC Control Register
704 AT91_REG ADC_MR; // ADC Mode Register
705 AT91_REG Reserved0[2]; //
706 AT91_REG ADC_CHER; // ADC Channel Enable Register
707 AT91_REG ADC_CHDR; // ADC Channel Disable Register
708 AT91_REG ADC_CHSR; // ADC Channel Status Register
709 AT91_REG ADC_SR; // ADC Status Register
710 AT91_REG ADC_LCDR; // ADC Last Converted Data Register
711 AT91_REG ADC_IER; // ADC Interrupt Enable Register
712 AT91_REG ADC_IDR; // ADC Interrupt Disable Register
713 AT91_REG ADC_IMR; // ADC Interrupt Mask Register
714 AT91_REG ADC_CDR0; // ADC Channel Data Register 0
715 AT91_REG ADC_CDR1; // ADC Channel Data Register 1
716 AT91_REG ADC_CDR2; // ADC Channel Data Register 2
717 AT91_REG ADC_CDR3; // ADC Channel Data Register 3
718 AT91_REG ADC_CDR4; // ADC Channel Data Register 4
719 AT91_REG ADC_CDR5; // ADC Channel Data Register 5
720 AT91_REG ADC_CDR6; // ADC Channel Data Register 6
721 AT91_REG ADC_CDR7; // ADC Channel Data Register 7
722 AT91_REG Reserved1[44]; //
723 AT91_REG ADC_RPR; // Receive Pointer Register
724 AT91_REG ADC_RCR; // Receive Counter Register
725 AT91_REG ADC_TPR; // Transmit Pointer Register
726 AT91_REG ADC_TCR; // Transmit Counter Register
727 AT91_REG ADC_RNPR; // Receive Next Pointer Register
728 AT91_REG ADC_RNCR; // Receive Next Counter Register
729 AT91_REG ADC_TNPR; // Transmit Next Pointer Register
730 AT91_REG ADC_TNCR; // Transmit Next Counter Register
731 AT91_REG ADC_PTCR; // PDC Transfer Control Register
732 AT91_REG ADC_PTSR; // PDC Transfer Status Register
810 AT91_REG SSC_CR; // Control Register
811 AT91_REG SSC_CMR; // Clock Mode Register
812 AT91_REG Reserved0[2]; //
813 AT91_REG SSC_RCMR; // Receive Clock ModeRegister
814 AT91_REG SSC_RFMR; // Receive Frame Mode Register
815 AT91_REG SSC_TCMR; // Transmit Clock Mode Register
816 AT91_REG SSC_TFMR; // Transmit Frame Mode Register
817 AT91_REG SSC_RHR; // Receive Holding Register
818 AT91_REG SSC_THR; // Transmit Holding Register
819 AT91_REG Reserved1[2]; //
820 AT91_REG SSC_RSHR; // Receive Sync Holding Register
821 AT91_REG SSC_TSHR; // Transmit Sync Holding Register
822 AT91_REG SSC_RC0R; // Receive Compare 0 Register
823 AT91_REG SSC_RC1R; // Receive Compare 1 Register
824 AT91_REG SSC_SR; // Status Register
825 AT91_REG SSC_IER; // Interrupt Enable Register
826 AT91_REG SSC_IDR; // Interrupt Disable Register
827 AT91_REG SSC_IMR; // Interrupt Mask Register
828 AT91_REG Reserved2[44]; //
829 AT91_REG SSC_RPR; // Receive Pointer Register
830 AT91_REG SSC_RCR; // Receive Counter Register
831 AT91_REG SSC_TPR; // Transmit Pointer Register
832 AT91_REG SSC_TCR; // Transmit Counter Register
833 AT91_REG SSC_RNPR; // Receive Next Pointer Register
834 AT91_REG SSC_RNCR; // Receive Next Counter Register
835 AT91_REG SSC_TNPR; // Transmit Next Pointer Register
836 AT91_REG SSC_TNCR; // Transmit Next Counter Register
837 AT91_REG SSC_PTCR; // PDC Transfer Control Register
838 AT91_REG SSC_PTSR; // PDC Transfer Status Register
916 AT91_REG US_CR; // Control Register
917 AT91_REG US_MR; // Mode Register
918 AT91_REG US_IER; // Interrupt Enable Register
919 AT91_REG US_IDR; // Interrupt Disable Register
920 AT91_REG US_IMR; // Interrupt Mask Register
921 AT91_REG US_CSR; // Channel Status Register
922 AT91_REG US_RHR; // Receiver Holding Register
923 AT91_REG US_THR; // Transmitter Holding Register
924 AT91_REG US_BRGR; // Baud Rate Generator Register
925 AT91_REG US_RTOR; // Receiver Time-out Register
926 AT91_REG US_TTGR; // Transmitter Time-guard Register
927 AT91_REG Reserved0[5]; //
928 AT91_REG US_FIDI; // FI_DI_Ratio Register
929 AT91_REG US_NER; // Nb Errors Register
930 AT91_REG US_XXR; // XON_XOFF Register
931 AT91_REG US_IF; // IRDA_FILTER Register
932 AT91_REG Reserved1[44]; //
933 AT91_REG US_RPR; // Receive Pointer Register
934 AT91_REG US_RCR; // Receive Counter Register
935 AT91_REG US_TPR; // Transmit Pointer Register
936 AT91_REG US_TCR; // Transmit Counter Register
937 AT91_REG US_RNPR; // Receive Next Pointer Register
938 AT91_REG US_RNCR; // Receive Next Counter Register
939 AT91_REG US_TNPR; // Transmit Next Pointer Register
940 AT91_REG US_TNCR; // Transmit Next Counter Register
941 AT91_REG US_PTCR; // PDC Transfer Control Register
942 AT91_REG US_PTSR; // PDC Transfer Status Register
1012 AT91_REG TWI_CR; // Control Register
1013 AT91_REG TWI_MMR; // Master Mode Register
1014 AT91_REG TWI_SMR; // Slave Mode Register
1015 AT91_REG TWI_IADR; // Internal Address Register
1016 AT91_REG TWI_CWGR; // Clock Waveform Generator Register
1017 AT91_REG Reserved0[3]; //
1018 AT91_REG TWI_SR; // Status Register
1019 AT91_REG TWI_IER; // Interrupt Enable Register
1020 AT91_REG TWI_IDR; // Interrupt Disable Register
1021 AT91_REG TWI_IMR; // Interrupt Mask Register
1022 AT91_REG TWI_RHR; // Receive Holding Register
1023 AT91_REG TWI_THR; // Transmit Holding Register
1067 AT91_REG TC_CCR; // Channel Control Register
1068 AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
1069 AT91_REG Reserved0[2]; //
1070 AT91_REG TC_CV; // Counter Value
1071 AT91_REG TC_RA; // Register A
1072 AT91_REG TC_RB; // Register B
1073 AT91_REG TC_RC; // Register C
1074 AT91_REG TC_SR; // Status Register
1075 AT91_REG TC_IER; // Interrupt Enable Register
1076 AT91_REG TC_IDR; // Interrupt Disable Register
1077 AT91_REG TC_IMR; // Interrupt Mask Register
1199 AT91_REG Reserved0[4]; //
1201 AT91_REG Reserved1[4]; //
1203 AT91_REG Reserved2[4]; //
1204 AT91_REG TCB_BCR; // TC Block Control Register
1205 AT91_REG TCB_BMR; // TC Block Mode Register
1231 AT91_REG PWMC_CMR; // Channel Mode Register
1232 AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
1233 AT91_REG PWMC_CPRDR; // Channel Period Register
1234 AT91_REG PWMC_CCNTR; // Channel Counter Register
1235 AT91_REG PWMC_CUPDR; // Channel Update Register
1236 AT91_REG PWMC_Reserved[3]; // Reserved
1260 AT91_REG PWMC_MR; // PWMC Mode Register
1261 AT91_REG PWMC_ENA; // PWMC Enable Register
1262 AT91_REG PWMC_DIS; // PWMC Disable Register
1263 AT91_REG PWMC_SR; // PWMC Status Register
1264 AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
1265 AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
1266 AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
1267 AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
1268 AT91_REG Reserved0[55]; //
1269 AT91_REG PWMC_VR; // PWMC Version Register
1270 AT91_REG Reserved1[64]; //
1301 AT91_REG UDP_NUM; // Frame Number Register
1302 AT91_REG UDP_GLBSTATE; // Global State Register
1303 AT91_REG UDP_FADDR; // Function Address Register
1304 AT91_REG Reserved0[1]; //
1305 AT91_REG UDP_IER; // Interrupt Enable Register
1306 AT91_REG UDP_IDR; // Interrupt Disable Register
1307 AT91_REG UDP_IMR; // Interrupt Mask Register
1308 AT91_REG UDP_ISR; // Interrupt Status Register
1309 AT91_REG UDP_ICR; // Interrupt Clear Register
1310 AT91_REG Reserved1[1]; //
1311 AT91_REG UDP_RSTEP; // Reset Endpoint Register
1312 AT91_REG Reserved2[1]; //
1313 AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register
1314 AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register
1382 #define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Regi…
1384 #define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
1385 #define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
1386 #define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
1387 #define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
1388 #define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
1389 #define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
1390 #define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
1391 #define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
1392 #define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
1393 #define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
1394 #define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
1395 #define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
1396 #define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
1397 #define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
1398 #define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
1399 #define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
1400 #define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
1401 #define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
1403 #define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register
1404 #define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
1405 #define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
1406 #define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
1407 #define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
1408 #define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
1409 #define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register
1410 #define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
1411 #define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
1412 #define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
1413 #define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
1414 #define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
1416 #define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1417 #define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1418 #define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1419 #define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1420 #define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1421 #define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1422 #define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1423 #define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1424 #define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1425 #define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1427 #define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
1428 #define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
1429 #define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
1430 #define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
1431 #define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
1432 #define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
1433 #define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
1434 #define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
1435 #define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
1436 #define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
1437 #define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
1438 #define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
1439 #define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
1440 #define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
1441 #define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
1442 #define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
1443 #define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
1444 #define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
1445 #define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register
1446 #define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
1447 #define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
1448 #define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
1449 #define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
1450 #define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
1451 #define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
1452 #define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
1453 #define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
1454 #define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
1455 #define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
1457 #define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
1458 #define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
1459 #define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
1461 #define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
1462 #define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
1463 #define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
1464 #define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
1465 #define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
1466 #define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
1467 #define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
1468 #define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
1469 #define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
1470 #define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
1471 #define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1472 #define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
1473 #define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
1474 #define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
1475 #define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
1477 #define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
1478 #define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
1479 #define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
1481 #define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
1482 #define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
1483 #define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
1484 #define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
1486 #define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
1487 #define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
1488 #define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
1489 #define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
1491 #define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
1492 #define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
1493 #define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
1495 #define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
1496 #define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
1497 #define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
1498 #define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
1499 #define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
1500 #define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
1502 #define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
1503 #define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
1504 #define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
1505 #define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
1506 #define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
1507 #define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
1508 #define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
1509 #define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
1510 #define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
1511 #define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
1513 #define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
1514 #define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
1515 #define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
1516 #define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
1517 #define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
1518 #define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
1519 #define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
1520 #define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
1521 #define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
1523 #define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
1524 #define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
1525 #define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
1526 #define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
1527 #define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
1528 #define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
1529 #define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
1530 #define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
1531 #define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
1532 #define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
1534 #define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
1535 #define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
1536 #define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
1537 #define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
1538 #define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
1539 #define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
1540 #define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
1541 #define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
1542 #define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
1543 #define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
1544 #define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
1545 #define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
1546 #define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
1547 #define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
1548 #define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
1549 #define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
1550 #define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
1551 #define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
1553 #define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
1554 #define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
1555 #define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
1556 #define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
1557 #define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
1558 #define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
1559 #define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
1560 #define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
1561 #define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
1562 #define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
1564 #define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
1565 #define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
1566 #define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
1567 #define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
1568 #define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register
1569 #define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
1570 #define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
1571 #define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
1572 #define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
1573 #define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
1574 #define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
1575 #define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
1576 #define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register
1577 #define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
1578 #define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
1579 #define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
1581 #define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
1582 #define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
1583 #define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
1584 #define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
1585 #define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
1586 #define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
1587 #define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
1588 #define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
1589 #define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
1590 #define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
1592 #define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register
1593 #define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
1594 #define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
1595 #define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
1596 #define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
1597 #define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
1598 #define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
1599 #define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
1600 #define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
1601 #define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
1602 #define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
1603 #define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
1604 #define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
1605 #define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
1606 #define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
1608 #define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
1609 #define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
1610 #define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
1611 #define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
1612 #define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
1613 #define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
1614 #define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
1615 #define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
1616 #define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
1617 #define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
1619 #define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
1620 #define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
1621 #define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
1622 #define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
1623 #define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
1624 #define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
1625 #define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register
1626 #define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
1627 #define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
1628 #define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
1629 #define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
1630 #define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
1631 #define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
1632 #define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
1633 #define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
1635 #define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
1636 #define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
1637 #define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
1638 #define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
1639 #define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register
1640 #define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
1641 #define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
1642 #define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
1643 #define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
1644 #define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
1645 #define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
1647 #define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
1648 #define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
1649 #define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
1650 #define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
1651 #define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / …
1652 #define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
1653 #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
1654 #define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
1655 #define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
1656 #define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
1658 #define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
1659 #define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
1660 #define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
1661 #define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
1662 #define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / …
1663 #define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
1664 #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
1665 #define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
1666 #define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
1667 #define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
1669 #define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
1670 #define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
1671 #define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
1672 #define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
1673 #define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / …
1674 #define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
1675 #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
1676 #define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
1677 #define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
1678 #define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
1680 #define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
1681 #define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
1683 #define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
1684 #define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
1685 #define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
1686 #define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
1687 #define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
1688 #define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
1690 #define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
1691 #define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
1692 #define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
1693 #define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
1694 #define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
1695 #define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
1697 #define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
1698 #define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
1699 #define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
1700 #define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
1701 #define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
1702 #define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
1704 #define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
1705 #define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
1706 #define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
1707 #define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
1708 #define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
1709 #define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
1711 #define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
1712 #define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
1713 #define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
1714 #define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
1715 #define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
1716 #define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
1717 #define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
1718 #define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
1719 #define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
1721 #define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
1722 #define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
1723 #define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
1724 #define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
1725 #define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
1726 #define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
1727 #define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
1728 #define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
1729 #define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
1730 #define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
1731 #define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register