Lines Matching refs:port
92 + Add Cortex-M35P port. Contributed by @urutva.
93 + Add embedded extension (RV32E) support to the IAR RISC-V port.
126 + Fix build warning in MSP430X port when large data model is used.
127 + Add the ability to use Cortex-R5 port on the parts without FPU.
134 + Fix build issue in POSIX GCC port on Windows Subsystem for Linux (WSL). Contributed
136 + Add portMEMORY_BARRIER to Microblaze port. Contributed by @bbain.
137 + Add portPOINTER_SIZE_TYPE definition for ATmega port. Contributed by @jputcu.
180 + Add vectored mode interrupt support to the RISC-V port.
181 + Add support for RV32E extension (Embedded Profile) in RISC-V GCC port.
223 + Add hardware stack protection support to MicroBlazeV9 port. This ensures that
234 + Add prototype for prvPortYieldFromISR to the POSIX port so that it builds
266 + Update the RL78 IAR port to the latest version of IAR which uses the
269 + Add tick type is atomic flag when tick count is 16-bit to PIC24 port. This
274 + Remove #error when RISC-V port is compiled on a 64-bit RISC-V platform.
276 + Fix ullPortInterruptNesting alignment in Cortex-A53 port so that it is
281 + Change FreeRTOS IRQ Handler for Cortex-A53 SRE port to store and restore
282 interrupt acknowledge register. This ensures that the SRE port behavior
283 matches the Memory Mapped IO port. Contributed by @sviaunxp.
313 + ARMv8-M secure-side port: Tasks that call secure functions from the
355 + Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from
357 + Correct a build error in the POSIX port.
391 + Add support for ESP IDF 4.2 to ThirdParty Xtensa port.
437 + New Renesas RXv3 port layer.
440 + Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in
441 the same way the Windows port layer enables FreeRTOS to run on Windows
460 + Added RISC-V port for the IAR compiler.
461 + Update the Windows simulator port to use a synchronous object to prevent
465 + Correct alignment of stack top in RISC-V port when
481 + Added contributed port and demo application for a T-Head (formally C-SKY)
508 + Added ARM Cortex-M23 port layer to complement the pre-existing ARM
509 Cortex-M33 port layer.
510 + The RISC-V port now automatically switches between 32-bit and 64-bit
529 + Added GCC RISC-V MCU port with three separate demo applications.
538 + Updated third party Xtensa port so it is MIT licensed.
540 compiler RX600v2 port to enable switching between platform.h and
541 iodefine.h includes within that port's port.c file.
590 + Added Xtensa port and demo application for the XCC compiler.
591 + Changed the implementation of vPortEndScheduler() for the Win32 port to
593 + Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect
661 in the MPU port.
671 + Improvements to the Win32 port including using higher priority threads.
673 + Updated GCC TriCore port to build with later compiler versions.
746 + Increase the priority of the Windows threads used by the Win32 port. As
749 prevent the Windows port executing on single core hosts.
763 + GCC ARM Cortex-A port: Introduced the configUSE_TASK_FPU_SUPPORT
766 + GCC ARM Cortex-A port: It is now possible to automatically save and
779 demonstrate how to use the updated MPU port.
786 + Add an ARM Cortex-M4F port for the MikroC compiler. Ensure to read the
787 documentation page for this port before use.
788 + MPS430X IAR port: Update to be compatible with the latest EW430 tools
790 + IAR32 GCC port: Correct vPortExitCritical() when
871 Cortex-M3 port layers.
879 + Added ARM Cortex-A53 64-bit port.
880 + Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx
897 + New PIC32MEC14xx port.
899 port.
900 + Zynq7000 port layer now declares the functions that setup and clear the
904 + Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is
905 currently the only port that uses it.
906 + Updates to RL78 and 78K0 IAR port layers to improve support for
932 + Added Intel IA32/x86 32-bit port.
943 + Add additional NOPs to the MSP430X port layers to ensure strict compliance
945 + Microblaze port: Added option for port optimised task selection.
946 + Microblaze port: Previously tasks inherited the exception enable state
949 + Windows port: Add additional safe guards to ensure the correct start up
951 + Windows port: Improve the implementation of the port optimised task
962 + Added demo project for the new IA32/x86 port that targets the Galileo
981 + Improve the NetworkInterface.c file provided for the Windows port of
992 + Some updates to the Xilinx Microblaze GCC port.
993 + Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio.
994 + Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a
996 use the ARM Cortex-M4F port.
999 Windows port.
1000 + Update the PIC32 port to remove deprecation warnings output by the latest
1060 + Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0
1062 + Cortex-A5 GIC-less port no longer passes the address of the interrupting
1075 + Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU.
1095 individual port layers where necessary so it does not affect ports that do
1131 + Fix a bug in the Tasking compiler's Cortex-M port that resulted in an
1137 + Updated the CCS Cortex-R4 port to enable it to be built with the latest
1144 + Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced.
1145 The new port is demonstrated on an Atmel SAMA5D3 XPlained board.
1225 + Add Cortex-A9 GCC port layer.
1251 + Added a port layer and a demo project for the new PIC32MZ architecture.
1252 + Update the PIC32MX port layer to re-introduce some ehb instructions that
1257 + Make dramatic improvements to the performance of the Win32 simulator port
1261 + Slight improvement to the Cortex-M4F port layers where previously one
1267 + Update the Cortex-M0 port layers to allow the scheduler to be started
1298 + Add Cortex-M0 port for Keil.
1299 + Updated Cortus port.
1351 Compatibility information for FreeRTOS port writers:
1386 + (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
1405 + Fix build error when R4 port is build in co-operative mode.
1406 + Multiple port and demo application maintenance activities.
1420 the yield macros of Cortex-M and Cortex-R port layers. For efficiency
1421 the Cortex-M port layer "yield" and "yield" from ISR are now implemented
1445 ARM Cortex-M3 port layers.
1451 + Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and
1459 + Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function
1466 + Minor optimisations to the PIC32 port layer.
1484 + Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to
1496 + Added port specific optimisations to the PIC32 port layer, and updated the
1498 + Added port specific optimisations to the Win32 simulator port.
1527 + Added a vQueueDelete() handler for the FreeRTOS MPU port (this was
1529 + Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to
1531 + Updated the prvReadGP() function in the NIOS II port to ensure the compiler
1553 used in the FreeRTOS MPU port.
1593 + Updated the FreeRTOS MPU port to be correct for changes that were
1597 + Tidy up various port implementations to add the static key word where
1604 + Changed the implementation of thread deletes in the Win32 port to prevent
1605 the port making use of the traceTASK_DELETE() trace macros - leaving this
1607 + Made some benign changes to the RX600 Renesas compiler port layer to
1645 + Cortex-M4F IAR port.
1646 + Cortex-M4F Keil/RVDS port.
1647 + TriCore GCC port.
1674 ports - including the new TriCore port where the checked pointer does not
1676 + The portCLEAN_UP_TCB() macro has been added to allow port specific clean
1677 up when a task is deleted - again this is required by the TriCore port.
1718 + The official FreeRTOS Renesas RX200 port and demo application have been
1720 + The official FreeRTOS Renesas RL78 port and demo application have been
1725 + A new Microblaze V8 port layer has been created to replace the older, now
1726 deprecated, port layer. The V8 port supports V8.x of the Microblaze IP,
1729 port layer. The demo application was created using V13.1 of the Xilinx
1748 not be retrofitted to existing ports until the existing port itself is
1755 + All ARM7 port layers have been slightly modified to prevent erroneous
1760 + The PIC32 port layer has been updated in preparation for V2 of the C32
1763 use the brand new Spartan-6 port and demo in its place.
1786 + Updated the RX600 port and demo applications to take into account the
1792 + Slightly changed the PIC32 port layer to move an ehb instruction in line
1820 + Updated the MSP430X IAR port and demo project to include support for the
1828 + Updated the PIC32 port layer to ensure the
1847 + Added a new port for the MSP430X core using the IAR Embedded Workbench.
1893 + Added port and demo application for the Cortus APS3 processor.
1910 + SuperH SH7216 (SH2A-FPU) port and demo application added.
1935 The following minor changes only effect the Cortex-M3 MPU port:
1991 + Added a new port and demo app for the Altera Nios2 soft core.
2011 + Added Virtex5 / PPC440 port and demos.
2023 + Added ColdFire V1 MCF51CN128 port and WEB server demo.
2025 + Changed the Cortex M3 port.c asm statements to __asm so it can be
2027 + Updated the Posix/Linux simulator contributed port.
2039 + Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a
2046 + Added in the lwIP port layer for the Coldfire MCF52259.
2066 PC port to instead use scheduler locks. This is because the BIOS calls
2072 + Added NEC V850ES port and demo.
2073 + Added NEC 78K0R port and demo.
2074 + Added MCF52259 port and demo.
2075 + Added the AT91SAM9XE port and demo.
2089 + Added IAR MSP430 port and demo.
2096 + Added a new port and demo application for the ColdFire V2 core using the
2099 Keil compiler with a new port that uses the new Keil/RVDS combo.
2104 + MSP430 port layers have been updated to permit tasks to place the
2107 + Replaced the two separate MSP430/Rowley port layers with a single and more
2115 + Completely re-written port for ColdFire GCC.
2128 ports and demos. See the port documentation pages on the FreeRTOS.org
2130 + Improved efficiency of Cortex M3 port even further.
2131 + Ensure the Cortex M3 port works no matter where the vector table is
2133 + Added the IntQTimer demo/test tasks to a demo project for each CM3 port
2149 + Updated the PIC32 port to allow queue API calls to be used from
2152 + Added a new PowerPC port that demonstrates how the trace macros can be
2157 + BUG FIX: The first PPC405 port contained a bug in that it did not leave
2199 + Efficiency gains within the PIC32 port layer.
2203 + Added a Virtex4 PowerPC 405 port and demo application.
2208 + Efficiency improvements to the Cortex-M3 port layer. NOTE: This
2214 M3 port layer (bringing it up to the same standard as the IAR and GCC
2221 + Added Fujitsu MB91460 port and demo.
2222 + Added Fujitsu MB96340 port and demo.
2235 + Updated STR9 uIP port to manually set the net mask and gateway addresses.
2281 + Updated the GCC port for the Cortex M3 to include the
2283 included in the IAR port.
2284 + Optimised the GCC and IAR port layer code - specifically the context
2295 + Updated the AVR32 port to ensure correct behaviour with full compiler
2297 + Included binaries for OpenOCD FTDI and parallel port interfaces.
2302 + Updated AVR32 UC3A port and demo applications.
2332 + Update to WizC PIC18 port to permit its use with version 14 of the
2350 + Added STR750 ARM7 port using the Raisonance RIDE/GCC tools.
2366 + Added STR750 port and demo.
2383 + Changed the critical section handling in the IAR AVR port to correct the
2410 + Added a port and demo application for the STR9 ARM9 based processors from
2418 + Added a port and demo application for the Cortex-M3 target using the IAR
2460 + Added a Luminary Micro port and demo for use with Rowley CrossWorks.
2467 + Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers.
2476 with every port:
2513 + GCC port now contain all assembler code in a single asm block rather than
2522 port.
2526 + Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above.
2528 + Added a new Microblaze port and demo application.
2553 + Added an IAR port for the Philips LPC2129
2580 One port just mirrors the existing GCC port. The other port was provided
2596 This release updates the HCS12 port. The common kernel code
2599 + Updated the HCS12 port to support banking and introduced a demo
2614 microcontrollers. Currently the HCS12 port is limited to the small
2617 + PIC18 wizC port updated. Thanks to Marcel van Lieshout for his
2619 + The accuracy of the AVR port timer setup has been improved. Thanks to
2641 + Each port now defines BaseType_t as the data type that is most
2651 + The AT91FR40008 ARM7 port contributed by John Feller is now included
2653 + The PIC18 port for the wizC/fedC compiler contributed by Marcel van
2655 + The IAR port for the AVR microcontroller has been upgraded to V3.0.0
2656 and is now a supported port.
2667 accommodate the wizC/fedC PIC port.
2670 directory and the IAR port in the Demo/AVR_ATMega323_IAR directory.
2680 specifically to the port being used. The application specific
2685 the demo application rather than being specific to the port.
2697 + The portheap.c file included with the AVR port has been deleted. The
2699 + The GCC AVR port is now build using the standard make utility. The
2722 + The MPLAB PIC port now saved the TABLAT register in interrupt service
2734 + AVR port - Replaced the inb() and outb() functions with direct memory
2735 access. This allows the port to be built with the 20050414 build of
2737 + GCC LPC2106 port - removed the 'static' from the definition of
2740 + GCC LPC2106 port - Corrected the optimisation options in the batch files
2799 port. Some optimisation levels use the stack differently to others. This
2802 tasks context. This allows the GCC ARM7 port to be used at all
2812 + Added the Keil ARM7 port.
2818 + Added the MSP430 port.
2819 + Extra comments added to the GCC ARM7 port.c and portISR.c files.
2850 + The ARM7 port now supports THUMB mode.
2851 + Modification to the ARM7 demo application serial port driver.
2855 + Rationalised the ARM7 port version of portEXIT_CRITICAL() -
2862 + Added the first ARM7 port - thanks to Bill Knight for the assistance
2878 + Added an AVR port that uses the IAR compiler.
2890 + Added Cygnal 8051 port.
2895 + Minor changes to prevent compiler warnings when compiling the new port.
2966 Barring the change to the interrupt vector (PIC port) these are minor
2978 + Reverted the Flashlite COM port driver back so it does not use the DMA.
2980 port was also calculating a register value incorrectly resulting in the
2991 Small fix made to the PIC specific port.c file described below.
3000 V1.2.4 contains a release version of the PIC18 port.
3016 + The ATMega port definition of portCPU_CLOSK_HZ definition changed to
3026 The zip file also contains a pre-release version of the PIC18 port. This
3034 portSTACK_GROWTH macro. This is required for the PIC port where the
3038 where it should have been since the creation of an eight bit port.
3053 files specific to the Borland compiler port.
3056 transmitted and received on the serial port. The Flashlite 186 demo
3072 The Flashlite 186 serial port driver has also been modified to use a DMA
3106 The majority of these changes were made to accommodate the 8bit AVR port.
3113 + Added AVR port.
3144 + Minor change to the Flashlite serial port driver. The driver is written
3180 + The Flashlite 186 port now uses 186 instruction set (used to use 80x86
3189 seems to have problems stepping over the call. This if for the PC port